ASML, TSMC to advance transition to large-format EUV photomasks
While High NA EUV will be adopted for production using the current 6-inch masks, the transition to larger, 12-inch masks is expected to further increase fab productivity, lower chipmaking costs and remove stitching constraints, benefiting the entire semiconductor industry.
ASML and TSMC have announced a collaborative initiative to lead the semiconductor industry’s transition to a larger-format Extreme Ultraviolet (EUV) lithography photomask.
While High NA EUV will be adopted for production using the current 6-inch masks, the transition to larger, 12-inch masks is expected to further increase fab productivity, lower chipmaking costs and remove stitching constraints, benefiting the entire semiconductor industry. It will enable advanced chip manufacturers to fully leverage the advantages of High NA EUV, making future generations of leading-edge chips more cost-effective, TSMC said.
“We expect the adoption of High NA EUV to increase progressively along the device scaling roadmap, first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanner productivity and allow the industry to meet the demand for smaller, faster and more energy-efficient chips,” said Christophe Fouquet, president & CEO, ASML. “We are pleased by the strong initial support of semiconductor manufacturers, mask suppliers and partners for this initiative.”
“We have always believed that when the industry works together to solve complex problems, we unlock possibilities that no single company could achieve alone,” said TSMC Chairman and CEO Dr. C.C. Wei. “By bringing together expertise from across the industry’s value chain, we hope to keep providing the benefits of cutting-edge technology through continuous innovation that lowers barriers and puts advanced solutions accessible at scale.”
TSMC intends to use ASML’s High NA technology in high-volume manufacturing for advanced nodes starting in 2030. As technology nodes advance, TSMC expects the number of layers requiring High NA EUV will rise, driven primarily by the increasingly complex transistor architectures required for AI applications, TSMC said.



