Software | June 11, 2008
Asset's ScanWorks integrated into Cadence Encounter Digital IC Design Flow
ASSET is working with Cadence Design Systems to integrate ASSETs ScanWorks platform into the Cadence Encounter Digital IC Design flow.
The integration will enable design and test engineers to embed instrumentation tools into complex, finished system-on-chip (SoC) and system-in-package (SiP) devices, providing deep analysis and test of these chips even after installation in the final product. The project kicks off immediately following the recent addition of Asset InterTech into the Cadence Connections partner program. The Cadence Connections Partner Program is available to makers of third-party software products that complement Cadence solutions and further enhance industry interoperability. Membership in the Cadence Connections program provides ASSET with access to Cadence software, documentation and support capabilities to facilitate the integration of ScanWorks embedded instrumentation tools into Cadences IC design, test and diagnostic flows. Cadences leadership in board and SiP package design will be leveraged to address the growing challenges of SiP and multi-chip module (MCM) device testing and diagnostics. Initial applications will provide tools and flows that support the preliminary IEEE P1687 Internal JTAG (IJTAG) standard.