Honda and Renesas sign agreement to develop high-performance SoC
Honda Motor and Renesas have signed an agreement to develop a high-performance system-on-chip (SoC) for software-defined vehicles (SDVs).
The new SoC is designed to deliver leading-edge AI performance of 2,000 TOPS combined with a power efficiency of 20 TOPS/W. It is slated for use in future models of the “Honda 0 (Zero) Series,” Honda’s new electric vehicle (EV) series, specifically those that will be launched in the late 2020s.
Honda is developing original SDVs to provide a mobility experience optimised for each customer in the Honda 0 Series. The Honda 0 Series will adopt a centralised E/E architecture that combines multiple electronic control units (ECUs) responsible for controlling vehicle functions into a single ECU. The core ECU, which serves as the heart of the SDV, manages essential vehicle functions such as Advanced Driver Assistance Systems (ADAS) and Automated Driving (AD), powertrain control, and comfort features, all on a single ECU. To achieve this, the ECU requires a SoC that provides higher processing performance than traditional systems, while minimising any increase in power consumption.
To realise Honda's vision for SDVs, the company reached an agreement with Renesas to develop a high-performance SoC compute solution designed for core ECUs. Using TSMC’s leading-edge 3-nm automotive process technology, this SoC also can achieve a significant reduction in power consumption. Additionally, it realises a system that utilises multi-die chiplet technology to combine Renesas’ generic fifth-generation (Gen 5) R-Car X5 SoC series with an AI accelerator optimised for AI software developed independently by Honda. The SoC chiplet solution will provide the AI performance required for advanced functions such as AD, while keeping power consumption low.
