Siemens accelerates AI chip verification with Nvidia technology

Siemens, in collaboration with Nvidia, has announced that its Veloce proFPGA CS hardware-assisted verification and validation system is empowering designers and system architects to create even more optimized designs by running and capturing trillions of verification cycles, prior to first silicon availability.

As part of their long-standing strategic partnership, Nvidia and Siemens have been able to capture tens of trillions of cycles over a span of just a few days by taking advantage of Siemens’ Veloce proFPGA CS scalable and performance-optimized hardware architecture and combining it with Nvidia’s performance-optimized chip architecture, Siemens said in a press release.

“Nvidia and Siemens are partnering in many areas, most recently in advancing hardware-assisted verification methodologies in general and FPGA-based prototyping in particular, to adapt to the verification and validation demands presented by highly complex AI/ML SoCs,” said Jean-Marie Brunet, senior vice president and general manager, hardware assisted verification, Siemens Digital Industries Software. “Veloce proFPGA CS is addressing these challenges by combining a highly flexible and scalable hardware architecture with an advanced, easy-to use implementation and debug software flow, enabling customers to always have the optimal solution for single-FPGA IP validation as well as for multi-billion gate chiplet designs.”

“As AI and computing architectures grow increasingly complex, semiconductor teams require high-performance verification solutions to validate massive workloads and accelerate time to market,” said Narendra Konda, vice president of hardware engineering, Nvidia. “The integration of Nvidia performance-optimized chip architectures with Siemens’ Veloce proFPGA CS enables designers to capture trillions of cycles in days, providing the scale needed to ensure reliability for the next generation of AI.”