Software | January 10, 2008
Cadence & Mentor launch open source OVM
Cadence Design Systems, Inc. and Mentor Graphics Corp. today announced immediate availability of the Open Verification Methodology (OVM).
The OVM, based on IEEE Std. 1800-2005 SystemVerilog standard, is the first open, language-interoperable, SystemVerilog verification methodology in the industry. The OVM provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. As a joint development initiative between Mentor Graphics® and Cadence Design Systems, the OVM is supported on multiple verification platforms ideally suited to both novice and expert verification engineers. “Open source, plug-and-play reuse, and multi-language support are the leading requests from our verification and training customers,” said Yoshiyumi Nagano, CEO of HD Lab. “We have reviewed other methodologies in the market, but only OVM offers this combination of capabilities. We are pleased to see the first release of the OVM source code and believe this will increase the efficiency.” The OVM includes the foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments and reusable Verification IP (VIP) in SystemVerilog. The OVM reduces the complexity of adopting SystemVerilog by embedding verification practices into its methodology and library, and significantly shortens the time to create verification environments, easily integrate plug-and-play VIP and ensure code portability and reuse.
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