Test & Measurement | September 05, 2007
ARM selects XJTAG system
ARM has selected the XJTAG boundary scan development system to improve and speed up the process of debugging and testing its range of ARM® RealView® development hardware tools, which include high-density, multi-layer development boards.
ARM is currently using XJTAG on its latest generation of RealView platform baseboards, which contain multiple high pin-count ball grid array (BGA) devices including processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). Spencer Saunders, engineering manager, platforms, System Design Division, ARM, said: “With tens of thousands of pins on each board, we recognised that it would not be possible to validate these circuits in a commercially realistic timescale without the use of a boundary scan test system. After evaluating the different competitive options, we selected the XJTAG boundary scan system due to its power, performance, versatility and cost effectiveness." The XJTAG system has enabled ARM to speed up the process of debug and test, get test coverage up to the 90 percent mark, achieve its ten-minutes-per-board boundary scan production test target, and to significantly improve production yields. Simon Payne, CEO at XJTAG, said: “We are delighted that ARM, the world's leading semiconductor intellectual property (IP) supplier, has selected the XJTAG system. With XJTAG, ARM engineers now have a boundary scan system that allows tests to be recorded, refined and repeatedly re-used throughout the development cycle both by its in-house team and contract manufacturing partners." ARM has developed a strong base of development tools, software and hardware products to support its system-on-chip IP. Its range of RealView development solutions are ideal systems for customers prototyping ARM processor-based products and are suitable for architecture and CPU evaluation, hardware and software development, and ASIC emulation. XJTAG's built-in design-for-test (DFT) functionality has enabled ARM to use the boundary scan system right from the very beginning of the development process to help improve the design and reduce respins. “XJTAG has saved ARM a great deal of time as it automatically handles any netlist changes by adapting to the new circuit connections, thereby avoiding the time-consuming process of manually picking through the netlist for errors," added Joao De Oliveira, VP of business development at XJTAG.
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