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Software | August 17, 2007

Mentor and Cadence offers Open SystemVerilog Verification Methodology

Cadence Design Systems, Inc. and Mentor Graphics Corp. today announced that they will standardize on a verification methodology based on the IEEE Std. 1800(tm)-2005 SystemVerilog standard.
The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability. It delivers on the promise of SystemVerilog with established interoperability mechanisms for Verification IP (VIP), transaction-level and RTL models, and full integration with other languages commonly used in production flows. The OVM will include a robust class library and be available in source code
format.

Cadence and Mentor have contributed both technology and resources to develop the foundation of the methodology and the libraries. The methodology will be made available under a standard open-source license, Apache(tm) License, Version 2.0.

"The OVM solves one of the biggest issues facing SystemVerilog adoption today," said Robert Hum, vice president and general manager of Mentor Graphics Design, Verification and Test Business Unit. "Customers seek confidence that their investments in verification will be reusable in the future. Having a methodology that works on a number of widely installed simulators and verification tools provides the confidence to move to SystemVerilog."

The OVM and supporting class library include the foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments, and reusable VIP in
SystemVerilog. The OVM reduces the complexity of adopting SystemVerilog by embedding verification practices into its methodology and library. The OVM will significantly shorten the time it takes to create verification environments, easily integrate verification IP and ensure code portability and reuse.

"With today's devices becoming more and more complex, engineers are under increasing pressure to speed deployment of verification methods," said Moshe Gavrielov, executive vice president and general manager, Cadence Verification Division. "With the OVM, Cadence and Mentor are delivering an efficient SystemVerilog-based tool-independent solution to help solve our combined customers' key design challenges. The industry as a whole will benefit with a much higher degree of interoperability, verification IP development and reuse, and ease of integration."

Open source licensing simplifies IP development and distribution Unlike some alternatives, the OVM library will be open source, SystemVerilog IEEE-1800 compliant, and portable to any simulator
supporting that IEEE standard. Under the terms of the Apache 2.0 license, it will also be easy for users and IP developers to re-ship the OVM code or derivatives and get support from multiple EDA vendors.

"The industry is clearly embracing SystemVerilog for functional verification, and this is further accelerated with an open source methodology that offers increased interoperability within the EDA
ecosystem," said Sanjay Srivastava, President and CEO at Denali Software. "Portability is key, and the OVM addresses this with multi-vendor support. The OVM and libraries are appealing to our broad verification IP customer base, and we will rapidly foster the transition to the OVM through our existing support for SystemVerilog and AVM. We've made a significant investment to develop a leading-edge SystemVerilog flow for our own design IP products, and will leverage the OVM to
further enhance our SystemVerilog leadership."

"The OVM offers exactly what we have been looking for: a single open, robust, and interoperable verification methodology," said Predrag Markovic, President of HDL Design House in Beograd, Serbia. "This greatly simplifies our development and support processes and will speed up the delivery of VIP and verification environment components to our customers. Customers will now benefit from plug-and-play verification IP. It's a win-win for everyone."

The OVM supports a unique mix of RTL and transaction-level abstractions for SystemVerilog and other high-level languages that support system-level design and verification. The next generation of
system-on-chip (SoC) design is already increasing customer demand in the area of transaction-level modeling and verification. This growing demand will include the need to combine software-based simulation, hardware-based verification platforms, and established transaction-level interface standards.

"Doulos is committed to be the premier supplier of education for the OVM as the demands of complex SoC design strain alternate verification technologies," said Robert Hurley, CEO Doulos. "The commitment from Cadence and Mentor to offer an open verification methodology rooted on IEEE 1800 with transaction-level modeling support that is interoperable amongst EDA tools and supports interoperable VIP will be matched by our commitment to support customers globally with training to allow them to get the most out of the OVM."
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