New JTAG Visualizer from GOEPEL

The new tools enable the real-time activation and analysis of individually defined logic states directly in the target hardware (Pin/Net Toggler) without prior test program generation. They automatically identify potentially unsafe or hardware harming vectors as well as logic states of non-Boundary Scan nets and pins (cluster logic). The new tool suite is complemented by interactive graphical visualizer SCAN VISION™ III, which has been developed with ASTER Technologies within the frame of an OEM agreement. In addition to the native schematic and layout cross probing, this tool offers the innovation to apply a data flow oriented, virtual schematic for interactive logic probing in a completely integrated development environment. “With the new tools we're the first vendor to close the gap between the requirements to graphically analyse logic states of the target hardware fast and flexible. Additionally, it's now possible to eliminate target hardware damages by faulty vectors and to involve non-Boundary Scan circuit parts into the verification at the same time“, Thomas Wenzel, Managing Director Boundary Scan Division at GOEPEL electronic gladly announces. “Based on the tight cooperation with ASTER Technologies, we're now able to enormously enhance our second generation Boundary Scan visualization capability. The entire solution sets new patterns in particular for a fast, flexible and safe prototype hardware verification (Rapid Prototype Test)". Christophe Lotz, Managing Director of ASTER Technologies said: “We are pleased to be associated with Goepel Electronics and have the opportunity to demonstrate the seamless integration of our advanced board viewing technology within SCAN VISION™ III. It is a clear indication of ASTER's continued commitment to work closely with the industry's leading test equipment suppliers."