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Electronics Production | March 09, 2005

Fraunhofer IIS Selects Mentor Graphics

Fraunhofer Institute for Integrated Circuits IIS, an audio and video research laboratory in Erlangen, Germany, has selected the Mentor Graphics Catapult C Synthesis tool for use in next-generation digital broadcast
applications.
After an evaluation comparing leading high-level synthesis tools, Fraunhofer IIS chose the Catapult C Synthesis tool based on quality of results, time savings, ease of use, and the tool's compatibility with the company's C/C++ design flow.

Fraunhofer IIS develops digital broadcast applications that depend on complex digital signal processing (DSP) algorithms. The organization typically implements the full system in field programmable gate arrays (FPGA) as a prototype for real-time performance validation before retargeting the design to an application specific integrated circuit (ASIC) for production. Manual register-transfer level (RTL) creation for FPGA prototypes and ASICs were found to be too inefficient and error prone, and left no time for design space exploration. This triggered the decision to explore high-level synthesis to reduce manual development time and validation effort.
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