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Electronics Production | December 04, 2006

STMicro's NAND flash now in 70nm

STMicroelectronics today announced full availability of its entire NAND Flash memory family in 70nm process technology. The transition of the 512-Mbit (Small Page) and 1/2/4/8-Gbit (Large Page) devices to ST's advanced 70nm manufacturing process establishes the family at the leading edge of NAND Flash technology, with lower prices and reduced power consumption.

The high density memory chips are designed to provide mass data storage in a range of computing and consumer applications, such as digital cameras, PDAs, GPS navigation systems, Flash cards and USB drives, printers, set-top boxes (STBs), digital TV sets, car multimedia systems, and mobile handsets with multimedia features. All the devices in the family provide ultra-fast data throughput and erase capability. The Address lines and Data Input/Output signals of all members of the family are multiplexed onto an 8-bit or 16-bit bus, reducing pin count and allowing the use of a modular NAND interface which enables systems to be adapted to use higher (or lower) density devices without changing the device footprint. A software tool chain available from ST enables the rapid development of products that use the new memory chips, and can also help to extend their useful life. Tools include Error Correction Code (ECC) software; Bad Block Management (BBM) to recognize and replace a block that fails an Erase or Program operation, by copying its data to a valid block; Wear Leveling algorithms to optimize the aging of the device by distributing Erase and Program operations among all the blocks; File System OS Native reference software; and hardware simulation models. Memory is organized into blocks that can be read and programmed by page. Each page contains a Spare Area, whose bytes are typically used for Error Correction Codes, software flags or Bad Block identification. A Copy Back Program mode enables data stored in one page to be programmed directly into another without the need for external buffering. A Block Erase command with an erase time of 2ms is provided. Each block is specified for 100,000 Program and Erase cycles, and 10-year data retention. Devices have a 'Chip Enable Don't Care' feature, which simplifies the microcontroller interface and streamlines the use of NAND Flash in combination with other types of memory such as NOR Flash and xRAM – memory combinations are often used where faster devices are needed for code and working memory, while using the much lower cost and higher density NAND memory for large file storage.
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