Industry edges closer to finalising HBM4 standard
JEDEC, the trade body for standards for the microelectronics industry, says it is 'nearing completion' of the next version of its High Bandwidth Memory (HBM) DRAM standard: HBM4.
The organisation says in a press release that the successor to the HBM3 standard will enhance data processing rates while maintaining essential features such as higher bandwidth, lower power consumption, and increased capacity per die and/or stack. These advancements are essential for applications that require efficient handling of large datasets and complex calculations – in other words AI, high-performance computing and servers.
JEDEC has more than 350 member companies that work across 100 committees to define standards that are accepted throughout the industry. Its HBM4 committee has now confirmed that HBM4 will introduce a doubled channel count per stack compared to HBM3, with a larger physical footprint. To support device compatibility, the standard will ensure that a single controller can work with both HBM3 and HBM4 if needed.
Different configurations will require various interposers to accommodate the differing footprints. HBM4 will specify 24Gb and 32Gb layers, with options for supporting 4-high, 8-high, 12-high and 16-high TSV stacks. The committee has reached initial agreement on speeds bins up to 6.4 Gbps and is now discussing higher frequencies.
