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Cu-Pillar Bumps - The Design-to-Market Solution
With demand increases for cheaper, smaller, faster, portable, and yet multi-featured electronic consumer devices/products, the demand of flip-chip (FC) technology in high-density packaging is growing rapidly.
With demand increases for cheaper, smaller, faster, portable, and yet multi-featured electronic consumer devices/products, the demand of flip-chip (FC) technology in high-density packaging is growing rapidly. With the device size reduced, the increase in device electrical current density and thermal energy density become inevitable. Very often, existing integrated circuit (IC) packages could not effectively manage the increased in electrical current and thermal energy density, thus hampering product reliability and/or features. Also with the miniaturization, the Input/Output (IO) pads on the ICs become smaller and closer (smaller pitch) to each other.
This brings about another challenge in using existing FC technology packaging with solder balls. Solder balls would link two separate adjacent IO pads together when the pitch becomes too small. In the foreseeable future, device miniaturization using conventional (solder ball) FC packaging solution may lead to, but not limit to, (1) serious electromigration reliability problem in FC interconnects resulted from higher electrical current density, and (2) heat trap or thermal runaway due to the thermal dissipation capability of current IC packages, (3) more input/output pads per silicon device, thus closer bumps to adjacent bumps. Many problems surfaced with the miniaturization, including that of assembly processes, can be minimized with the implementation of Copper Pillar (Cu-pillar) bump into existing IC packages. Cu-pillar bump, which is shown in Figure 1, comprises of two segments - a Copper base and a solder tip. It has superior electrical and thermal characteristic over the conventional solder ball, and it could take form to flexible shapes to effectively resolve the problems that come with the increased in electrical current and thermal energy density. An emerging FC packaging technology using Cu-Pillar bumps (as shown in Figure 1) to replace solder ball bump is expected to minimize, if not eliminate, some of the problems faced by the current solder-ball based packaging technology. Figure 2 illustrates the implementation of the Cu pillar in one of the FC packaging technology - QFN (Quad Flat Nolead) package.
Cu Pillar Electrical Current Capacity Advantage
The emerging of FC packaging technology is inevitable with the increasing demand for miniaturization. Existing FC packaging technology using solder ball for interconnect as shown in Figure 3 suffers reliability issues dominated by the electromigration, which is worsen with the demand for higher electrical current density. Figure 3 shows the electromigration voids created near silicon are due to the electrons direction flow and also the very high density of electrical current at the failure locality. With the same amount of electric current passing through the Cu-Pillar bump, a longer time would be require to form such electromigration voids. Because the electromigration voids at the Cu-Pillar bump were created away from the current crowding region
near the device metal trace. The electrical current density at the current crowding region could be as high as 10 times than that of the bump average as noted by some studies.
Cu-Pillar Thermal Advantage
The continual increase of devices' operating speed and devices' miniaturization has pushed some devices' heat to an unbearable level. A number of devices turn to FC technology packaging to deal with the thermal issue. These devices are mostly lateral transistors typed devices, whose heat is generated near the device surface (pad side). However, solder ball based FC packaging technology is limited by the amount of area on the device that the solder ball could contact. Because solder balls could not be placed near together, the contact area on the device by the solder ball is limited, and so is the heat dissipation. Unlike solder ball bumps, Cupillar bumps could be placed closer together thus increasing the contact area to dissipate more heat. Additionally, Cu-Pillar bumps could take up any form of shapes as illustrated in Figure 5, more contact area is possible and more thermal dissipation paths from the device surface through Cu-Pillar bumps to the
board/chassis. Hence, through Cu-Pillar, devices could maintain a lower operating temperature and thus lesser energy loss.
Cu-Pillar Assembly Process Advantages
Fine-Pitch Flip-chip Packaging
With pad pitch getting smaller, conventional FC packaging would face solder ball bridging challenges as illustrate in Figure 6(a). To avoid bridging, smaller solder balls could be used as shown in Figure 6(c). However, using smaller solder balls result in low standoff flip-chip assembly, which is critical to reliability and underfill process. Cu-Pillar bumps could resolve the fine-pitch issue because it consists of a non-reflowable copper segment to maintain a higher standoff during flip-chip assembly. Higher standoff assembly facilitates the capillary and/or the direct mould underfilling process and thus minimizing voids forming.
No Solder-Paste Printing Process
High-lead solder ball, which has high melting temperature, are utilized in the FC packaging to prevent standoff collapse during flip-chip. However, utilization of high-lead solder ball would require the challenging solder-paste printing process for interconnecting to the leadframe. The reflowable solder tip on the Cu-Pillar structure enables the interconnection without additional solder paste printing process.
Controlled Solder Spreading
The solder ball reflowable characteristic required selective surface finishing on leadframe to prevent solder overflow or overspreading that result in standoff flip-chip assembly to collapse. For Cu-Pillar bump in the FC assembly, the leadframe does not required selective surface finishing to prevent overspreading, because amount of solder tip is controlled. Figure 7 (a) shows that the solder spreading of the Cu-Pillar bump is controlled. The controlled solder spreading characteristic enable the use of non-selective solder mask substrate as illustrate in Figure 7 (b), whose solder mask opening is large and not selective to individual pads. The solder mask selective openings, which are not required for Cu-Pillar bumps technology, are mainly used to controlled the solder spreading of solder balls in the substrate technology. The mask openings of the substrate are often
the limiting factor for fine-pitch pads substrate. Together with the Cu-Pillar bump technology, FC assembly onto substrate is possible for fine-pitch devices like DRAM chips. Furthermore, non-selective mask opening would simplify the substrate fabrication process and cost saving on the substrate.
Consistent Assembled Cu-Pillar Bump in FC Packaging
During the conventional FC assembly process, solder balls reflowed to inconsistent structures as shown inFigure 8. The inconsistent structure would leads inconsistent space between different bumps even with careful design of the bump layout. The different gaps encourage underfill material to fill the larger gaps and avoid the smaller gaps. Thus, resulting in voids in the final package or assembly, which latter translate to reliability issue. Cu-Pillar bump minimizes the inconsistent space among the bumps due to it's non-reflowable copper segment as clearly shown in Figure 7 (a). Hence, voids would be minimized and reliability improved.
Conclusion
It is likely that conventional FC packaging technology would no longer meet the demand for further
miniaturized packaged product. The Cu-Pillar technology incorporating into FC packaging technology not only meets the demand for product miniaturization, it also improves product features with its excellent electrical, and thermal characteristic. Furthermore, the Cu-Pillar bump technology could simplify various assembly process and thus increase the assembly productivity and resulting further saving of cost.
Cu Pillar Electrical Current Capacity Advantage
The emerging of FC packaging technology is inevitable with the increasing demand for miniaturization. Existing FC packaging technology using solder ball for interconnect as shown in Figure 3 suffers reliability issues dominated by the electromigration, which is worsen with the demand for higher electrical current density. Figure 3 shows the electromigration voids created near silicon are due to the electrons direction flow and also the very high density of electrical current at the failure locality. With the same amount of electric current passing through the Cu-Pillar bump, a longer time would be require to form such electromigration voids. Because the electromigration voids at the Cu-Pillar bump were created away from the current crowding region
near the device metal trace. The electrical current density at the current crowding region could be as high as 10 times than that of the bump average as noted by some studies.
Cu-Pillar Thermal Advantage
The continual increase of devices' operating speed and devices' miniaturization has pushed some devices' heat to an unbearable level. A number of devices turn to FC technology packaging to deal with the thermal issue. These devices are mostly lateral transistors typed devices, whose heat is generated near the device surface (pad side). However, solder ball based FC packaging technology is limited by the amount of area on the device that the solder ball could contact. Because solder balls could not be placed near together, the contact area on the device by the solder ball is limited, and so is the heat dissipation. Unlike solder ball bumps, Cupillar bumps could be placed closer together thus increasing the contact area to dissipate more heat. Additionally, Cu-Pillar bumps could take up any form of shapes as illustrated in Figure 5, more contact area is possible and more thermal dissipation paths from the device surface through Cu-Pillar bumps to the
board/chassis. Hence, through Cu-Pillar, devices could maintain a lower operating temperature and thus lesser energy loss.
Cu-Pillar Assembly Process Advantages
Fine-Pitch Flip-chip Packaging
With pad pitch getting smaller, conventional FC packaging would face solder ball bridging challenges as illustrate in Figure 6(a). To avoid bridging, smaller solder balls could be used as shown in Figure 6(c). However, using smaller solder balls result in low standoff flip-chip assembly, which is critical to reliability and underfill process. Cu-Pillar bumps could resolve the fine-pitch issue because it consists of a non-reflowable copper segment to maintain a higher standoff during flip-chip assembly. Higher standoff assembly facilitates the capillary and/or the direct mould underfilling process and thus minimizing voids forming.
No Solder-Paste Printing Process
High-lead solder ball, which has high melting temperature, are utilized in the FC packaging to prevent standoff collapse during flip-chip. However, utilization of high-lead solder ball would require the challenging solder-paste printing process for interconnecting to the leadframe. The reflowable solder tip on the Cu-Pillar structure enables the interconnection without additional solder paste printing process.
Controlled Solder Spreading
The solder ball reflowable characteristic required selective surface finishing on leadframe to prevent solder overflow or overspreading that result in standoff flip-chip assembly to collapse. For Cu-Pillar bump in the FC assembly, the leadframe does not required selective surface finishing to prevent overspreading, because amount of solder tip is controlled. Figure 7 (a) shows that the solder spreading of the Cu-Pillar bump is controlled. The controlled solder spreading characteristic enable the use of non-selective solder mask substrate as illustrate in Figure 7 (b), whose solder mask opening is large and not selective to individual pads. The solder mask selective openings, which are not required for Cu-Pillar bumps technology, are mainly used to controlled the solder spreading of solder balls in the substrate technology. The mask openings of the substrate are often
the limiting factor for fine-pitch pads substrate. Together with the Cu-Pillar bump technology, FC assembly onto substrate is possible for fine-pitch devices like DRAM chips. Furthermore, non-selective mask opening would simplify the substrate fabrication process and cost saving on the substrate.
Consistent Assembled Cu-Pillar Bump in FC Packaging
During the conventional FC assembly process, solder balls reflowed to inconsistent structures as shown inFigure 8. The inconsistent structure would leads inconsistent space between different bumps even with careful design of the bump layout. The different gaps encourage underfill material to fill the larger gaps and avoid the smaller gaps. Thus, resulting in voids in the final package or assembly, which latter translate to reliability issue. Cu-Pillar bump minimizes the inconsistent space among the bumps due to it's non-reflowable copper segment as clearly shown in Figure 7 (a). Hence, voids would be minimized and reliability improved.
Conclusion
It is likely that conventional FC packaging technology would no longer meet the demand for further
miniaturized packaged product. The Cu-Pillar technology incorporating into FC packaging technology not only meets the demand for product miniaturization, it also improves product features with its excellent electrical, and thermal characteristic. Furthermore, the Cu-Pillar bump technology could simplify various assembly process and thus increase the assembly productivity and resulting further saving of cost.
