© aleksandr volkov dreamstime.com Analysis | September 10, 2013
Chip carrier packaging grows
Advanced packaging of semiconductor chips has emerged as a key enabler in many of today’s electronic system products.
Put another way, package selection is increasingly important to the success of the end product. While much attention with regard to IC packaging is on 3D stacking and integration technologies, there is another area of packaging that has quietly been flourishing during the past decade-and-a-half. Introduced in 1998, the quad flat no-lead (QFN) package design (including the related dual-sided DFN) has enjoyed phenomenal growth from the very beginning. With its low cost, small size, and excellent thermal and electrical performance characteristics, the QFN quickly became the mainstream package of choice for many low-to-medium I/O count ICs. In the past decade, new dual-row and even triple-row technologies have enabled QFNs to support many more I/Os and, thus, enter a wider range of IC product segments. Today, the QFN is one of, if not the, most widely used IC package types. IC Insights forecasts that the continuous high growth in demand for QFN-type packages will help push the flatpack/chip carrier (FP/CC) category of packages past the “old” small outline (SO) group of packages for the first time ever in 2013. The QFN is a type of chip carrier. The SO packages emerged in the early 1980s and then grew to become the industry’s most widely used package type by 1995. The FP/CC packages emerged around the same time and they offered higher I/O capabilities than the SO packages because they had leads on all four sides. The QFN package category in the JEDEC standards includes a variety of manufacturer-specific designs such as the MicroLeadFrame (MLF) package from Amkor, Fujitsu’s Bumped Chip Carrier (BCC) and small outline no-lead (SON) packages, Carsem’s Micro Leadframe Package (MLP), and ASE’s microchip carrier (MCC). There are similar JEDEC standards for DFN packages that have external bond pads or “lands” on two sides instead of four like the QFN. Besides being categorized in the FP/CC group of packages, QFNs and DFNs are also considered part of a larger group of packages called leadframe CSPs, or chip-scale packages. © IC Insights QFN and DFN packages are inexpensive to manufacture—they typically don’t have solder balls, are targeted at low-I/O applications (typically <85), and make use of pre-plated leadframes. Either wirebonds or flip-chip bumps are used to attach the IC to the leadframe. Versions like the MLF and BCC have an exposed die-attach paddle on the bottom of the package, which serves as an excellent thermal path away from the chip as well as a good ground-plane if the pad is grounded on the circuit board. That, in conjunction with the high electrical performance offered by short I/O connections, has made these leadframe CSPs attractive for use in packaging RF circuits for cellphones and other wireless and portable product applications. Many companies have migrated from SO-type packages to QFNs and DFNs and their popularity continues to spread as new advancements make QFNs/DFNs capable of handling a greater amount of circuitry and functionality. The QFNs with dual rows of lands can support as many as 180 I/Os. There are also a growing variety of QFNs/DFNs such as versions with multiple chips stacked inside, or types that have an air-cavity designed into the package for high-frequency microwave applications.
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