NEO unveils 1T1C and 3T0C IGZO-based 3D X-DRAM tech
Built on a 3D NAND-like architecture and with proof-of-concept test chips expected in 2026, the new 1T1C and 3T0C designs combine the performance of DRAM with the manufacturability of NAND.
NEO Semiconductor, a US-based developer of innovative technologies for 3D NAND flash memory and 3D DRAM, has announced the latest advancement in its 3D X-DRAM technology family — the industry-first 1T1C- and 3T0C-based 3D X-DRAM cell, a solution designed to deliver unprecedented density, power efficiency and scalability for the most demanding data applications, the company said.
Built on a 3D NAND-like architecture and with proof-of-concept test chips expected in 2026, the new 1T1C and 3T0C designs combine the performance of DRAM with the manufacturability of NAND, enabling cost-effective, high-yield production with densities up to 512Gb — a 10x improvement over conventional DRAM, according to a media release.
“With the introduction of the 1T1C and 3T0C 3D X-DRAM, we are redefining what’s possible in memory technology,” said Andy Hsu, Founder & CEO of NEO Semiconductor. “This innovation pushes past the scaling limitations of today’s DRAM and positions NEO as a frontrunner in next-generation memory.”
NEO Semiconductor’s technology platform now includes three 3D X-DRAM variants: 1T1C (one transistor, one capacitor) – The core solution for high-density DRAM, fully compatible with mainstream DRAM and HBM roadmaps; 3T0C (three transistor, zero capacitor) – Optimized for current-sensing operations, ideal for AI and in-memory computing; and 1T0C (one transistor, zero capacitor) – A floating-body cell structure suitable for high-density DRAM, in-memory computing, hybrid memory and logic architectures.
