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PCB | November 09, 2010

Mentor Graphics & ARM join forces on memory test & repair

Mentor Graphics Corporation has teamed up with ARM to provide an automated memory test and repair solution for ARM embedded memories and processor cores.
The new capability provides full interoperability between Mentor’s Tessent memory test and repair solution and ARM’s family of cores and embedded memory IP.

“The requirements for embedded memories are increasing as design complexity and demand for feature rich functionality grow,” said Simon Segars, executive vice president and general manager, ARM physical IP division. “An effective memory test and repair solution is critical to ensuring high quality levels and maximum product yield. We are pleased to be working with Mentor to ensure a robust memory test and repair solution is available to our mutual customers.”

In order to maximize performance, ARM now includes an optimized memory BIST bus and interface that provides external access to all memories contained within the processor core. This integrated feature enables normally intrusive memory BIST IP to be placed outside the core, removing any impact to processor performance. Mentor's recently introduced Tessent memory BIST and self-repair solution has been enhanced to fully support this interface. The Tessent MemoryBIST product automatically configures, generates and integrates memory BIST and self-repair IP that operates with an ARM processor core's specific bus and embedded memories.

The Tessent solution also supports ARM memory compiler features. ARM has developed the capability to generate a complete Tessent memory view for memory instances generated by their compilers supporting TSMC 40nm and Common Platform 32/28nm processes. This interoperability enables a fully automated flow for adding Tessent test and repair functionality to ARM embedded memories contained anywhere within a design or processor core.
“With the huge complexity involved in testing the latest processor-based SoCs, designers need as much automation as possible to ensure that testing does not become the bottleneck in getting new designs to market,” said Joseph Sawicki, vice president and general manager for the Design-to-Silicon division at Mentor Graphics. “At the same time, they cannot afford to skimp on the quality of test. This integration between Tessent and ARM technologies gives customers what they need to deliver the most advanced, defect-free IC products to market in a timely manner.”

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