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SMT & Inspection | January 20, 2009

JTAG/Boundary Scan reduces test cost on complex boards

Phil Randall is a satisfied man and looking at the test equipment he’s working with at ACW Technology, you can see why. With a staff of around 350, ACW is a Contract Electronics Manufacturer providing a complete product manufacturing, logistics and repair service.
Complex and technically advanced products are manufactured, tested and configured into systems. The Company’s customers are, among others, professional Digital TV system providers as well as companies from the telecom, radio communication, aerospace and military sectors. For the latter, ACW’s services include environmental, vibration and HASS testing.

The company runs two facilities: one in South-England (Southampton) and one in South-Wales, production work is done at both sites, but tests for all sites are developed at the Southampton facility. The Company develops and manufactures a large range of different products mainly of small or medium batches (high-mix/value, low-volume).

Phil Randall works at the Southampton site. As senior test development engineer he’s been dealing with test strategies and technologies for many years. In former times most ACW products were designed for an In-Circuit Test bed of nails. In those days ICT was the best solution as the volumes were higher and board density was lower. But batches became smaller and boards became increasingly dense. Phil has an ICT background, but found the new technologies were gradually making bed-of-nails testing impractical. Thus, he started to investigate alternative test technologies. In the late 1990s he moved towards Flying Probe test with JTAG/Boundary Scan where possible. ACW boards had significantly changed throughout the years. In the early 2000’s they had 5,000-10,000 nets on the boards with “modern” component types such as FPGAs or CPLDs. Phil Randall decided to utilise the Boundary Scan technology more intensively as the required Boundary Scan architecture was now being routinely included in many modern component types. “FPGAs are an overriding technology on customers boards today and almost always have Boundary Scan”, commented Phil.



Consequently, test engineers at ACW moved over to a Flying Probe test with complementary Boundary Scan. First they executed the FPT followed by Boundary Scan. Additionally, Boundary Scan enhanced test coverage as more and more digital components and nets arrived on the boards. Phil Randall concluded: “Boundary Scan has come of age” and they also took advantage of ICT with in-built Boundary Scan. Even though they found many benefits, the system was “lacking in performance and difficult to implement effectively on large boards”. Moreover the constant reduction of test access for ICT lead to the decision to apply Boundary Scan as a stand-alone tool.

In Phils opinion that was the best choice, as Boundary Scan offers an integrated environment, its own library and a comprehensive programming language. He explains: “Nail access went out of the window and bed of nails became impossible on some products”. He began an excercise to evaluate the most suitable Boundary Scan system for ACW and obtained two Boundary Scan systems for comparative evaluation. The Goepel system was quickly chosen over the competitor due to the fully integrated environment and comprehensive libraries “SYSTEM CASCON is much easier to handle and, additionally, offers helpful features such as net list merger. One requirement was the definition of pin state – and with the GOEPEL system that became easily possible.”



Now test engineers at ACW had found the right system and some of its benefits are:
• Integrated environment
• Libraries – full device behaviour modelling and handling of individual pins
• New component Models available quickly from Goepel applications support
• Intuitive working methods
• Features such as Component Explorer, NetBrowser or Advanced Vector Browser (AVB) and Debugger.
The latter give a quick overview of the applied test vectors with detected faults highlighted. The pin and net level information in the AVB is scalable to allow an overview or in-depth investigation into individual pins and nets.

Even though test time is very short it’s not critical, since test coverage is more important. Phil Randall says: “Zero defects mean satisfied customers”. But being a Contract Manufacturer, the time to develop tests is crucial as well and the results they achieve with the GOEPEL system have been more than satisfactory.

ACW initially creates an Interconnect Test. This particular test checks conductor tracks connected to Boundary Scan nets for shorts, Stuck-At High, Stuck-At Low, disconnected tracks or pull resistors. All compliant products will be tested with interconnect as an absolute minimum “Interconnection is crucial”, says Phil Randall. “It’s a great feature of the GOEPEL system that the scan path is automatically built from the netlist”.



ACW Technology Ltd. has always striven to produce boards of the highest quality. Since 2004 this high quality is assured by one of the most advanced test systems they could purchase. Phil Randall is a satisfied customer. He’s happy that money was spent well on the right product. “It’s the best Boundary Scan system available that we have seen and Goepel seem intent on continually taking it forwards.” Test capability would have been limited without the GOEPEL system. He additionally compliments the support. Whenever he contacts the vendor in case of problems or difficulties he immediately gets help. “We’ve always been satisfied”, Phil says and adds: “Anyway why would we use equipment from anyone else but the European market leader? What else can I say.”



Ultimately, ACW knows that anyone not using Boundary Scan risks losing important opportunities in an increasingly competitive market. Opportunities that define success or failure in the market: time, money and a technical advantage.

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