Test & Measurement | March 12, 2008

evertiq speaks to XJTAG CEO Simon Payne

evertiq has spoken to Mr. Simon Payne, CEO of UK based supplier of IEEE 1149.1 JTAG compliant boundary scan development systems, XJTAG, and asked about the development within the boundary scan test solution market in Europe.
How well spread in Europe is the usage of products such as XJTAG's boundary scan solutions?

Answer: The increased density of boards and the trend towards ball grid array (BGA) packages is driving a worldwide demand for boundary scan systems. This market growth is backed up by Frost and Sullivan researchers who analysed the world market for printed circuit automatic test equipment, and found that boundary scan test solutions would be an important factor driving growth from US$970.1 million in 2004 to US$1.55 billion by 2011.

XJTAG is now selling globally - and with more and more distributors being appointed (there are already approaching 30 - see, sales are forecast to continue.

What errors or faults are not discoverable in PCBs, BGAs or entire circuits with XJTAG's boundary scan tools?

Answer: No test solution can test all of a design but as XJTAG tests both JTAG and non-JTAG devices, it is often possible - with a well designed board - to see test coverage very close to 100%. However, some designs will need a number of test solutions to achieve an acceptable level of test which is why XJTAG has a Technology Partner programme.

When you get the information from the boundary scan, how is that information used for the design and the industrialization of the products?

Answer: XJTAG provides a test solution across the whole product life cycle from design to manufacture and servicing. The real benefits start from early in the design cycle - even before any hardware is produced.

Just by using the design files it is possible to get a "design for test" analysis of your board. This can show up early design faults (and hopefully allow you to have these corrected before PCB layout is completed), as well as allowing you to modify your design to ensure that there is enough test coverage in preparation for production. At this stage alone, complete board respins can be avoided thereby reducing a product's time to market.

When your first prototype board/s arrives, the files that you generated for your "design for test" analysis can now be re-used to check the design and verify that the board has been assembled correctly. This can also help circumvent any hardware-software designer conflicts that sometimes arise when something is not working correctly.

Once the test and debug stage is completed, the test system can be handed over to the production facility for manufacturing testing.

How tough is the competition within XJTAG's business segment?

Answer: XJTAG provides a test solution across the whole product life cycle, and by providing reusable code and the ability to test non-JTAG devices, the test development time and cost is reduced. There are very few solutions in the market that take this approach.

The ones that may be confused about the names JTAG and XJTAG, what can you tell them to clear out their confusion about the similar names?

Answer: JTAG stands for Joint Test Action Group and is the usual name for the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture. JTAG or boundary scan testing allows a high proportion of populated printed circuit boards - particularly those featuring BGA devices - to be tested without using test probes. XJTAG, is the name of our IEEE 1149.1 boundary scan development system.

What will happen in the near future? Are you planning to enter any new markets or develop any new technologies?

Answer: XJTAG will continue to enhance its boundary scan development system to further abstract engineers from the complexity of the IEEE 1149.1 standard. We will continue to expand our distributor network and plan to extend our 'XJTAG-Inside' programme by integrating XJTAG with other test solution providers' systems through our Technology Partner programme.
Load more news
January 17 2019 2:20 pm V11.11.0-1