Microchip to develop spaceflight processor for NASA
NASA chooses Microchip Technology to develop the next-generation space-qualified compute processor platform to boost the performance of space computers.
NASA’s Jet Propulsion Laboratory in Southern California has selected Microchip Technology to develop a High-Performance Spaceflight Computing (HPSC) processor that will provide at least 100 times the computational capacity of current spaceflight computers – a capability that would advance all types of future space missions.
Niki Werkheiser, director of technology maturation within the Space Technology Mission Directorate at NASA Headquarters in Washington, states in a press release that such a cutting-edge spaceflight processor will have a tremendous impact on future space missions and even technologies back home on Earth.
“This effort will amplify existing spacecraft capabilities and enable new ones and could ultimately be used by virtually every future space mission, all benefiting from more capable flight computing.”
Work will take place under a USD 50 million firm-fixed-price contract, with Microchip contributing significant research and development costs to complete the project. Microchip will architect, design, and deliver the HPSC processor over three years, with the goal of employing the processor on future lunar and planetary exploration missions.
“We are pleased that NASA selected Microchip as its partner to develop the next-generation space-qualified compute processor platform.” says Babak Samimi, corporate vice president for Microchip’s Communications business unit, in the press release. “We are making a joint investment with NASA on a new trusted and transformative compute platform. It will deliver comprehensive Ethernet networking, advanced artificial intelligence/machine learning processing and connectivity support while offering unprecedented performance gain, fault-tolerance, and security architecture at low power consumption.”