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Application Notes |
Manipulating MCU SPI interface to access a non-standard SPI ADC
Question: Can I access a nonstandard SPI interface with my MCU?
Answer: Yes, but it might take a little extra effort.
Introduction
Many current precision analog-to-digital converters (ADCs) have a serial peripheral interface (SPI) or some serial interface to communicate with controllers including a microcontroller unit (MCU), a DSP, or an FPGA. The controllers write or read ADC internal registers and read conversion codes. SPI is becoming more and more popular due to its simple printed circuit board (PCB) routing and a faster clock rate compared to parallel interface. And, it is easy to connect an ADC to the controller with a standard SPI.
Some new ADCs have an SPI, but others have a nonstandard 3-wire or 4-wire SPI as a node because they want to achieve a faster throughput rate. For example, the AD7616, AD7606, and AD7606B family has two or four SDO lines for faster throughput rate in serial mode. The AD7768, AD7779, and AD7134 families have multiple SDO lines and they work as SPI mains. Users tend to encounter difficulties in designing microcontroller SPIs for ADC configuration and code reading.
Figure 1. AD7768 as a serial main with two data output pins (14001-193).
Standard MCU SPI Connection to an ADC
SPI is a synchronous, full-duplex, main/node-based interface. The data from the main or the node is synchronized on the rising or falling clock edge. Both main and node can transmit data at the same time. Figure 2 shows a typical 4-wire MCU SPI interface connection.
Figure 2. Standard MCU SPI connection to an ADC node.
To begin SPI communication, the controller must send the clock signal and select the ADC by enabling the CS signal, which is usually an active low signal. Since SPI is a full-duplex interface, both the controller and ADC can output data at the same time via the MOSI/DIN and MISO/DOUT lines, respectively. The controller SPI interface provides the user with flexibility to select the rising or falling edge of the clock to sample and/or shift the data. For reliable communication between the main and the node, users must follow the digital interface timing specifications of both the microcontroller and the ADC chip.
Figure 3. Example SPI data clock timing diagram.
If the microcontroller SPI and ADC serial interface have the standard SPI timing mode, it is not a problem for users to design the PCB routing and develop the drive firmware. But there are some new ADCs with a serial interface port that is not a typical SPI timing pattern. It does not seem possible for the MCU or the DSP to read data through the AD7768 serial port, a nonstandard timing SPI port, as shown in Figure 4.
Figure 4. AD7768 FORMATx = 1× timing diagram output on DOUT0 only.
This article will introduce approaches to manipulating the standard microcontroller SPI to interface with ADCs that have nonstandard SPI ports.
This article will cover four different solutions to read the ADC codes by serial interface:
About the Author: Steven Xie has worked as a product applications engineer with the China Design Center in © ADI Beijing since March 2011. He provides technical support for SAR ADC products across China. Prior to that, he worked as a hardware designer in wireless communication base stations for four years. In 2007, Steven graduated from Beihang University with a main’s degree in communications and information systems. He can be reached at steven.xie@analog.com.
- Solution 1: MCU as SPI node interfacing to ADC as SPI main by one DOUT line.
- Solution 2: MCU as SPI node interfacing to ADC as SPI main by two DOUT lines.
- Solution 3: MCU as SPI node interfacing to ADC as SPI main through DMA.
- Solution 4: MCU as SPI main and SPI node to read data on two DOUT lines.
- AD7768 works as the SPI main, so the STM32F429I SPI must be configured as SPI node.
- DRDY high pulse is just one cycle of DCLK duration that is not a typical CS.
- DCLK continuously outputs and DRDY is low when all the channel data bit output is finished.
- Configure one of STM32F429 is SPI ports, like SPI4, as a node to receive data bits on MOSI at DCLK.
- Connect AD7768 DRDY to the STM32F429 external interrupt input pin EXTI0 and NSS (SPI CS) pin. The rising edge of DRDY will trigger EXTI0 handler routine to enable the SPI node to start to receive data bits from the first DCLK falling edge after DRDY goes to low. Timing design is critical here.
- After all the data from Channel 0 to Channel 7 are received, the SPI should be disabled to prevent reading in extra invalid data, since the DRDY makes SPI node CS low and DCLK keeps toggling.
- Dhaker, Piyu. “Introduction to SPI Interface.” Analog Dialogue, Vol 52. September 2018.
- RM0090 Reference Manual: STM32F405/415, STM32F407/417, STM32F427/437 and STM32F429/439 Advanced ARM®-Based 32-Bit MCUs. STMicroelectronics, February 2019.
- STM32F427xx Data Sheet. STMicroelectronics, January 2018.
- UM1670 User Manual: Discovery Kit with STM32F429ZI MCU. STMicroelectronics, September 2017.
- Usach, Miguel. AN-1248 Application Note: SPI Interface. Analog Devices, Inc., September 2015.
About the Author: Steven Xie has worked as a product applications engineer with the China Design Center in © ADI Beijing since March 2011. He provides technical support for SAR ADC products across China. Prior to that, he worked as a hardware designer in wireless communication base stations for four years. In 2007, Steven graduated from Beihang University with a main’s degree in communications and information systems. He can be reached at steven.xie@analog.com.