ARM and Cadence collaborate

The initial solution optimizes ARM POP intellectual property (IP) technology, using the Cadence Encounter digital platform, for the Cortex-A9 processor on the TSMC 40LP process, including ultra low threshold voltage (uLVT). The resulting solution is available for license from ARM to accelerate the implementation of ARM processors. POP IP is comprised of core-hardening acceleration technology which incorporates the latest ARM Artisan advanced physical IP to achieve industry-leading power, performance and area (PPA) metrics. In the combined solution, the POP IP is tightly coupled to Cadence Encounter RTL-to-GDSII technologies, including RTL Compiler-Physical and the breakthrough clock concurrent optimization (CCOpt) design technology, resulting in market-leading, certified benchmarks for Cortex-A9 implementations using POP IP. This is the latest milestone in the companies' longstanding collaboration to enable their mutual customers to more efficiently design advanced SoCs. ARM is working closely with the Cadence R&D and Design Services organizations prior to the introduction of new POP IP to ensure that customers benefit from the quickest deployment of new ARM processors and/or new process technologies. Extending to TSMC 28HPM, the ARM-Cadence collaboration includes single, dual and quad-core implementations of Cortex-A9 and Cortex-A15 processors. "As customers face ever-increasing pressure to achieve specific power and performance numbers, our early engagement with Cadence helps ensure that customers choosing our POP IP solutions can achieve higher performance at a lower power than previously available," said Dr. John Heinlein, vice president of marketing, Physical IP Division at ARM. "The extensive implementation knowledge and comprehensive set of benchmarking results that ARM provides in POP technology, combined with a silicon-proven Cadence methodology, also enables customers to dramatically improve their time-to-market." POP solutions are comprised of three critical elements necessary to achieve an optimized ARM processor implementation. First, it contains Artisan physical IP standard cell logic and memory cache instances that are specifically tuned for a given ARM processor and foundry technology. Second, it includes a comprehensive benchmarking report to document the exact conditions and results ARM achieved for the processor implementation across an envelope of configuration and design targets. Finally, it includes the detailed implementation knowledge including floor plans, scripts, design utilities and a POP Implementation Guide, which enables the end customer to achieve similar results quickly and with lower risk. The Cadence Encounter RTL-to-GDSII flow helps design teams optimize power, performance, and area for the world's most advanced high-performance, energy-efficient ARM processor-based designs. The integrated Cadence flow includes Encounter RTL Compiler, Encounter Digital Implementation System, and signoff-proven Cadence QRC Extraction, and Encounter Timing System. In addition, the CCOpt technology unifies clock tree synthesis with logic/physical optimization resulting in significant power, performance and area improvements. "Working closely with the ARM engineering team, we have been able to deliver industry-leading performance, power and area for advanced ARM-processor implementations," said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. "The result of this combined effort enables customers to deliver the highest quality of silicon while meeting aggressive time-to-market goals."