Cadence enable successful tape out of 20nm SoC test chip

Engineers from the two companies collaborated closely using the Cadence solutions to overcome implementation and DFM verification challenges to complete the design. During development, GUC utilized the Cadence Encounter solution to support all of the complex steps in a 20nm place and route flow, including double patterning library preparation, placement, clock tree synthesis, hold fixing, routing and post route optimization. GUC also utilized Cadence Litho Physical Analyzer for DFM verification, turning the uncertainty of 20nm process variations into predictable impacts that helped reduce the design cycle. "We selected Cadence as a partner for this development because of their proven success at advanced nodes," said Kevin Tseng, Director of design methodology division at GUC. "The successful tape out of this 20nm SoC test chip on a TSMC process is a direct result of our close collaboration and the capabilities of the Cadence Encounter and DFM solutions." "As customers move to 20nm, they are faced with new challenges such as double patterning and process variations that greatly increase risk," said Dr. Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. "Cadence has addressed these advanced node challenges in both our implementation as well as DFM verification tools. The company is working closely with partners to validate these new flows to reduce risk and make it easier for customers to move to the 20nm process node with confidence."