© cumypah dreamstime.com Components | July 10, 2013
Xilinx tapes-out more 'Industry-Firsts'
Xilinx, Inc. announced two more industry firsts at 20nm, expanding on a series of industry innovations started at 28nm.
Xilinx has now taped out the semiconductor industry’s first 20nm device, and the PLD industry’s first 20nm All Programmable device. Xilinx has also implemented the industry’s first ASIC-class programmable architecture called UltraScale™. These milestones expand on Xilinx’s industry first 28nm tape-out, All Programmable SoCs, All Programmable 3D ICs, and SoC-strength design suite. “With the industry’s most aggressive 20nm tape-out schedule, I believe Xilinx is much greater than a year ahead of our nearest competition for high-end devices and about a half a year ahead for mid-range devices,” said Victor Peng, SVP of Programmable Products Group. “When you combine TSMC’s technology, our UltraScale architecture, and co-optimization with our Vivado® Design Suite, we believe we are about a year ahead in delivering 1.5–2X more realizeable system-level performance and integration—an equivalent to a generation ahead of our competition.” Xilinx has worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process, just as it had done in the development of 28HPL. The 28nm collaboration resulted in the industry’s first 28nm tape-out and the industry’s first All Programmable FPGA, SoC, and 3D IC devices, putting Xilinx a generation ahead in price/performance/watt, programmable systems integration, and BOM cost reduction. Xilinx has now extended this proven formula for industry leadership from 28nm to 20nm, resulting in the industry’s first tape-out of the first ASIC-class programmable architecture: UltraScale. The UltraScale architecture was developed to scale from 20nm planar, through 16nm and beyond FinFET technologies, and from monolithic through 3D ICs. It not only addresses the limitations to scalability of total system throughput and latency, but directly attacks the number one bottleneck to chip performance at advanced nodes: the interconnect. An innovative architectural approach is required to manage multi-hundred gigabit-per-second levels of system performance with smart processing at full line rate, scaling to terabits and teraflops. The mandate is not simply to increase the performance of each transistor or system block, or scale the number of blocks in the system, but to fundamentally improve the communication, clocking, critical paths, and interconnect to address the massive data flow and real-time packet, DSP, and/or image processing. The UltraScale architecture addresses these challenges by applying leading-edge ASIC techniques in a fully programmable architecture:
- Massive data flow optimized for wide buses that support multi-terabit throughput
- Multi-region ASIC-like clocking, power management, and next generation security
- Highly optimized critical paths and built-in high-speed memory, cascading to remove bottlenecks in DSP and packet processing
- Step function in inter-die bandwidth for 2nd generation 3D IC systems integration
- Massive I/O and memory bandwidth with dramatic latency reduction and 3D IC wide memory-optimized interface
- Elimination of routing congestion and co-optimization with Vivado tools for >90% device utilization without degradation in performance
- 400G OTN with intelligent packet processing and traffic management
- 4X4 Mixed Mode LTE and WCDMA Radio with smart beamforming
- 4K2K and 8K displays with smart image enhancement and recognition
- Highest performance systems for intelligence surveillance and reconnaissance (ISR)
- High performance computing applications for the data center
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