© cumypah Components | March 08, 2013

Atotech collaborates with Georgia Tech PRC

Atotech has expanded its collaboration with the 3D Systems Packaging Research Center (PRC), housed in the Manufacturing Research Center building on the Georgia Tech campus.
System on Package (SoP) eliminates the gap between Integrated Circuits (IC’s), Packages and Boards. The progress at IC level has been phenomenal with 32 nm technology now commonplace with 16 nm nodes and below coming to the market. This leaves an IC to package gap in lithography terms of at least 104 or in the order of one billion times. The vision of SoP therefore is to eliminate this IC-System gap using nanoscale materials, processes and the unique properties that they produce for every component of the system.

Georgia Tech enjoys the benefits of this collaboration. "PRC has benefited greatly from Atotech’s expertise and considerable investment in new process research in metallization, surface modification and surface finish technologies," states Venky Sundaram, PhD, Research Professor and Director of Research Programs at the 3D Systems Packaging Research Center at Georgia Tech.

"Specific benefits in recent years include a state-of-the-art 300 mm x 300 mm SoP panel plating tool at Georgia Tech, advanced electroless copper plating on smooth glass surfaces for interposer applications, high speed copper electroplating for fine pitch through via fill, and Ni-Pd-Au surface finish for low temperature Cu-Cu interconnections. The PRC’s cutting edge R&D programs in glass and Si interposers and ultra-thin organic packages for 3D PoP have benefited significantly in reducing our R&D cycle times due to the constant on-site support from product and research experts from Atotech Berlin, USA and Japan."

Development Highlights

Glass interposers are of very high interest to the packaging industry, to replace organic interposers and packages as they offer the potential to:
  • Increase the Input / Output terminations (I/O’s) by 10 x over current organic packages
  • Reduce the high Coefficient for Thermal Expansion (CTE) mismatch to the Si IC
  • 10x lower cost than a wafer silicon interposer
  • Offer improved thermal conductivity versus organic packages

A major highlight in the past year has been in developing a void-free through via fill process in fine pitch (70-100 μm) vias in thin organic laminate substrates, resulting in a “chiplast” embedded IC package with a total thickness of 130 μm, with equivalent I/O density and performance to a comparable fan-out wafer level package (FO-WLP), with significant benefits over eWLB such as intermediate testability, repair and compatibility with existing supply chain business models.
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