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Components | June 08, 2012

Hitachi employs Mentor Graphics’ platform

Hitachi, Ltd. (Chiyoda-ku, Tokyo) has adopted the Olympus-SoC place and route system for large scale ASIC development and has achieved successful tape out of a 40nm, 90 million gate design.
“Hitachi was able to easily close timing for this large scale 90 million gate design using the large flat mode capacity of Olympus-SoC,” said Kazuhisa Miyamoto, senior director, Monozukuri Innovation Group, Hardware Monozukuri Division, Information & Telecommunication Systems Company, Information & Telecommunication Systems Group, Hitachi, Ltd.

“Not only did Olympus make it easier and faster to close the design, but we also got much better quality of results. Through good communication with R&D, Mentor Graphics provided us with swift support whenever we got into trouble. We believe it is truly significant for our business that we completed such a successful tape out with Olympus-SoC.”

“Many place and route tools based on older architectures are out of steam at 40nm and 28nm, where designers face 100M gate design complexity along with high performance and low power challenges,” said Pravin Madhani, general manager of the Place and Route group at Mentor Graphics. “The Olympus-SoC architecture is built to address the capacity, performance and low-power requirements of smaller geometry nodes. Olympus-SoC also has tight links with Calibre, enabling designers to create “first time right” designs that meet all the signoff requirements of the target foundry without costly design iterations.”

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