Components | June 05, 2012
Cortus extends family of 32 bit RISC microcontroller IP cores
Cortus extends its family of 32 bit modern RISC microcontroller IP cores with the high performance APS5, aimed at more complex embedded systems on chip requiring caches and/or co-processors and is capable of multi-processor configuration.
The Cortus APS5 is a high performance, high throughput, 32-bit processor designed for complex embedded systems and features a high performance integer unit and an instruction cache. It is the third member of the Cortus microcontroller IP core family to be released in 2012 complementing the smaller energy efficient APS3R and the larger floating point FPS6. “The APS5 delivers very good computational performance and scalability making it suitable for more complex embedded subsystems”, said Michael Chapman, CEO and President of Cortus. He adds, “Despite its modest CPU core area, the APS5 delivers 2.29 DMIPS/MHz”. In common with other Cortus processors, the APS5 has a 5 to 7 stage integer pipeline and out-of-order completion ensuring that most integer instructions (load and stores included) are executed in a single cycle. Michael Chapman explains, “The APS5 architecture enables a high maximum clock frequency, for example it is capable of greater than 400 MHz in a 90 nm technology”.© Cortus The APS5 has been designed to provide scalable computing performance and is supplied with an instruction cache and a data cache is optional. Performance can be increased with symmetric multi-processing (SMP) configurations such as dual- or quad-core. For example, while a single APS5 core offers 1.93 CoreMarks/MHz a dual-core configuration benchmarks at 3.51 CoreMarks/MHz. For SMP configurations a coherent data cache with snoopy protocol is available. Other applications may benefit from heterogeneous APS5/APS3R configurations. As a member of the Cortus family of processors, APS5 interfaces to all of Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. It also shares the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead. Bridges to and from AHB-Lite and to APB ensure easy interfacing to other IP. The APS toolchain and IDE (for C and C++) is available to licensees free of charge, and which can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium μC/OS and μCLinux.
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