Components | February 07, 2012

Cadence collaborates with Samsung Foundry

Cadence collaborates with Samsung Foundry to deliver Design-for-Manufacturing solution for 32-, 28- and 20-nanometer chip design.
Samsung Electronics' Foundry business, Samsung Foundry, has collaborated with Cadence Design Systems to develop a design-for-manufacturing (DFM) infrastructure to produce the most advanced chips.

Working closely together, Cadence and Samsung Foundry have developed "in-design" and signoff DFM flows to tackle physical signoff and electrical variability optimization for 32-, 28- and 20-nanometer SoC designs. The new flows address both random and systematic yield issues, providing customers with a proven foundry option for advanced-node designs built on the Cadence Encounter digital and Cadence Virtuoso custom/analog implementation solutions.

"As we expand our customer base at advanced process nodes, customers require various design flows," said Kyu-Myung Choi, senior vice president of Infrastructure Design Center, Samsung Electronics, "By teaming with Cadence to build a strong foundry ecosystem for advanced node designs, we've achieved numerous benefits we can pass along to our customers such as reducing risk and speeding time to market. We've enjoyed great success at 32 and 28 nanometers with Cadence, and we have now extended our advanced DFM flow to 20 nanometers as well."

"As the provider of cutting-edge technologies and methodologies for leading foundries, we worked closely with Samsung Foundry to integrate our robust DFM suite, which continues to gain momentum as the advantages of in-design DFM become increasingly evident," said Tom Beckley, senior vice president, Custom IC and Signoff, Silicon Realization Group at Cadence. "The flows and underlying infrastructure our companies created together can provide a significant competitive edge by enabling engineers to meet tight deadlines while reducing the risk of costly errors."


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