Components | October 10, 2011
eSilicon and MIPS: Tapeout of 28nm 1.5GHz microprocessor cluster
eSilicon Corporation, the largest independent semiconductor value chain producer (VCP), and MIPS Technologies announced the tapeout of a high-performance, three-way microprocessor cluster on Globalfoundries’ low-power 28nm-SLP process technology.
Wafers are currently running in Globalfoundries’ Fab1 in Dresden, Germany, with silicon expected in early 2012. SoC designs can start immediately. MIPS provided the RTL based on its MIPS32 1074Kf Coherent Processing System (CPS), and eSilicon performed the synthesis and timing-driven layout, optimizing the design to achieve true worst-case performance of 1GHz for the cluster. Typical performance is expected to be approximately 1.5GHz.
"We worked closely with eSilicon on this project to not only demonstrate the capabilities of the high-performance 1074K CPS in a new low-power process, but also to enable our customers to use the resulting implementation in their SoC designs", said Gideon Intrater, vice president of product marketing and applications, MIPS Technologies.To reach the 1GHz target without compromising low power, eSilicon’s custom memory team created custom fast cache instances (FCIs) for the L1 caches to replace standard memories that were in the critical path of the design. The 1074Kf CPS is based on the combination of two high-performance technologies—coherent multiprocessing, and the superscalar, Out-of-Order (OoO) MIPS32 74K processor core as the base CPU. The 74K core is a multi-issue, 15-stage OoO architecture already in production with numerous customers for digital televisions, set-top boxes and a variety of home networking applications. It is broadly used in internet-connected digital home products. Customers can license the 1GHz implementation from eSilicon today—either as is or customized. The cluster has been taped out as a test chip, and will be offered as a hard macro core. It includes embedded design-for-test (DFT) and design-for-manufacturing (DFM) features so that it can be dropped into a chip design and used without modification. As part of a full SoC development, it can be further customized and optimized to meet the specific needs of the application. Go to the eSilicon website for more information on the 28nm high-performance, low-power three-way microprocessor cluster. “The 1074K CPS provides an ideal high-performance platform for today’s SoC designs, with headroom for tomorrow’s designs. We worked closely with eSilicon on this project to not only demonstrate the capabilities of the high-performance 1074K CPS in a new low-power process, but also to enable our customers to use the resulting implementation in their SoC designs. We are pleased that eSilicon will be making the design available off-the-shelf, as well as customized by its team of highly skilled engineers,” said Gideon Intrater, vice president of product marketing and applications, MIPS Technologies. “This was an exciting project for our custom IP engineers. Our custom FCIs did the trick in enabling us to meet the fast-approaching shuttle date. Together with the high quality of the MIPS 1074K design, we were able to quickly meet the challenging performance targets in a low-power process,” said Paul Hollingworth, eSilicon VP of strategic marketing. “eSilicon is looking forward to embedding this cluster into SoC designs for our customers to help them achieve a truly compelling combination of high performance, low price and low power.” ----- © MIPS
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