Components | September 16, 2011

Vitesse and Aliathon collaborate on 40G/100G OTN

Aliathon will license Vitesse Semiconductor’s patented portfolio of 40G and 100G hard decision eFEC cores for its FPGA and ASSP solutions aimed at emerging OTN applications.
Widely applied in fiber optic communications, eFEC reduces bit error rate in typically noisy signal environments. Developing cost-effective, improved signal-to-noise ratio solutions becomes a significant challenge as metro and long-haul networks transition up to 100G data rates and beyond.

Vitesse solves this issue with its patented Continuously Interleaved BCH (CI-BCH) eFEC code which offers the highest performing hard decision eFEC available today and is the industry’s only eFEC implementable in FPGA form at 100G.

“With optical networks rapidly evolving to accommodate growing bandwidth demands, service providers are focused on lower cost and power per bit in their metro and long-haul 100G systems."
"Vitesse's CI-BCH eFEC technology enables 40G and 100G backbones to operate over longer spans with lower power, lower cost, and lower latency. We are excited to add Aliathon to the growing ecosystem of OEMs, ASSP and FPGA solution providers using CI-BCH technology to implement high-density 40G and 100G Optical Transport solutions", said Steve Perna, vice president of product marketing at Vitesse.

“Providing industry-leading eFEC technology is a critical component in Aliathon’s OTN strategy,” said Alan McDade, commercial director at Aliathon. “Part of Aliathon’s value to our clients is rapidly adapting to new requirements in the OTN network. Working with today’s leader in OTN eFEC technology is testament to that fact. The combination of Aliathon’s framing, mapping and muxing technology for OTN with the Vitesse eFEC offers our clients a flexible, feature rich, high performance, cost effective and power efficient solution. Aliathon’s intention is to tightly couple Vitesse’s technology with our own and roll out a range of 100G OTN products throughout Q4-2011.”

Vitesse’s 40G/100G eFEC Cores

The Vitesse 40G/100G eFEC core portfolio is based on Vitesse’s patented CI-BCH eFEC technology. CI-BCH represents a breakthrough in block coding forward error correction technology necessary for optimal signal-to-noise ratio at these high data rates.

Major advantages of the CI-BCH eFEC code include:

-Ability to optionally configure to tradeoff coding gain for reduced eFEC decoder latency in sensitive applications, and

- Ability to occupy the lowest device resources of any eFEC code in the marketplace.

The 100G 7% and 20% overhead ratio cores occupy only 27% and 54% of available Lookup Table (LUT) resources in a Xilinx Virtex 6 FPGA, respectively, meaning that 100G OTN Muxponder and Transponder solutions can be created in a single FPGA. The 7% and 20% coding overhead versions provide up to 9.35dB and 10.5dB NECG, respectively.

At 100G operation and 7% overhead ratio, the Vitesse CI-BCH-3™ three error correcting eFEC core delivers 9.35dB NECG at an output bit error rate of 1x10E-15 and <10us decoder latency, better performance than any existing 7% overhead G.975.1 FEC cores on the market.

For 100G operation and 20% overhead ratio, the Vitesse CI-BCH-4™ four error correcting eFEC core delivers up to 10.5dB NECG at an output bit error rate of 1x10E-15 and <10us decoder latency.


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