Components | August 29, 2011
GloFo 2<sup>nd</sup>: Cooperation with Mentor
Mentor Graphics announced new capabilities in its design to silicon solutions that support Globalfoundries’ third generation of signoff-ready design enablement for IC manufacturing.
New technologies support Globalfoundries’ manufacturing analysis and scoring (MAS) methodology, which is implemented using the Calibre platform’s critical feature analysis (CFA), and can be used to optimize IP blocks and SoCs at all layers to help reduce the manufacturing variability of SoC products. The Calibre platform also supports Globalfoundries’ DRC+ pattern-based design rule checking technology, which identifies potential yield-limiting litho patterns while maintaining significant performance improvement over full litho simulation approaches. Other advances included in the third-generation DFM offering are new Calibre LFD™ kits for 28nm and 20nm, improved CMP models for 28nm, and improved interaction with place and route tools (such as the Mentor Olympus-SoC tool) and other design flows to prevent late-stage signoff violations. “The beauty of the Mentor solution is that it provides a single, consistent environment for managing the interface between designers and the fab throughout the life cycle of a manufacturing process node,” said Andy Brotman, vice president, Design Infrastructure, Globalfoundries. “Foundries use Calibre early in technology development to validate new process design rules, and to determine the specific patterns that require tighter design rule constraints. In the case of Globalfoundries, these rules and patterns are then transferred to our mutual customers in the form of DRC+ decks that integrate rules and patterns into a consistent, high performance verification environment. Globalfoundries MAS scoring methodology, based on Calibre CFA, in conjunction with the rest of the Calibre DFM platform, assures that third-party IP certified by Globalfoundries is resistant to manufacturing variability. Likewise, the same platform allows customers to evaluate the IP they develop themselves for their designs, reducing the risk of late stage problems that can lead to late products or slower than expected yield ramps", he continued.
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