The validated technologies in the 3D-IC solution span the Cadence Encounter RTL-to-signoff and Virtuoso custom/analog platforms. Also included are the Cadence system-in-package products, and recently acquired Sigrity power-aware chip/package/board signal integrity solution that helps engineers overcome die-stacking and silicon carriers' challenges from planning through implementation, test, analysis and verification.

TSMC's unique CoWoS combo bump cells, which simplify bump assignment, are now supported automatically in the Cadence Encounter Digital Implementation (EDI) System, QRC Extraction, and Cadence Physical Verification System. The CoWoS Reference Flow is supported with a CoWoS design kit and silicon validation results from a TSMC test vehicle.

TSMC chose Cadence's high bandwidth, low power Wide I/O controller and PHY Design IP solution to connect the SoC to Wide I/O DRAM using CoWoS technology featuring a peak data rate of over 100Gbit/sec for memory interface.

"The Cadence 3D-IC technology enables the next generation of high-performance mobile devices, and offers significant benefits in system performance and power efficiency," said Chi-ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. "Our continued work with TSMC on the CoWoS™ process ensures that the infrastructure is in place to support this important emerging technology."

"TSMC continues to work closely with Cadence to bring 3D-IC to the industry," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "We have invested three years with OIP ecosystem partners to prepare the CoWoS™ design flow for production, and now we're ready to enable customers' 3D-IC designs with TSMC CoWoS™ technology."