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Electronics Production | September 16, 2004

No barrier to entry at 90nm design rules

Graham Curren, founder of Sondrel Ltd, a European backend IC design consultancy, claims that with mask costs decreasing and design experience growing, that there is no longer any barrier to entry for companies wishing to use 90nm IC design processes.
He explains: “Designers want to take advantage of the shrinking die sizes and lower power consumption that 90nm technology delivers. But until recently, there have been two significant barriers to entry: cost and design cycle time due to the increased complexity of the layout.” One of those factors, cost, is being significantly reduced as 90nm mask prices have halved.

Continues Curren: “As 90nm becomes accepted as a more stable node, mask and other associated costs are falling. The other big stumbling block has been a lack of expertise in the new design challenges that users of 90nm design rules face.” Noise, On Chip Variation (OCV), and leakage are the biggest issues. Whereas at larger geometries these were often regarded as insignificant effects – or more commonly, not identified amongst other yield worries – at 90nm, it is essential to consider and make provision for inaccuracies caused by noise and OCV.

Another issue is design size. Whereas 90nm designs may well include many million standard cells, EDA tools, according to Curren, are still only realistically capable of handling blocks of up to 2-300 000 cells, which means that careful partitioning and hierarchical implementation must be performed.

Increasing design complexity has led to an increasing trend for companies to use specialist, expert consultancies. Details Curren: “Most of our customers are either using 90nm processing already, or they plan to within six months, and they are very keen to work with companies who have been successful in overcoming the unique challenges that this technology presents. We have five 90nm chips taped out and are working on three more.”

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