Electronics Production | May 29, 2006

Mentor recognized by STMicro

STMicroelectronics Certifies Mentor Graphics Catapult C Synthesis Libraries and Joins Silicon Vendor Partners Program.
Mentor Graphics Corporation today announced that STMicroelectronics has added Catapult® C Synthesis libraries to its standard ASIC (application specific integrated circuit) design kit, a premier status achieved only after extensive testing. This marks the first time STMicroelectronics has included high-level synthesis technology in its ASIC design kit, making electronic system level (ESL) design methodologies accessible to ASIC designers throughout the world.

"Catapult C Synthesis is now a proven tool that helps accelerate the development of high quality signal processing hardware," said Philippe Magarshack, FTM group vice president, Central CAD & Design Solutions General Manager, STMicroelectronics. "Catapult C libraries are the first high-level synthesis technologies to satisfy our stringent standards and we now want to extend the benefits of high-level synthesis to our customers who need to develop sophisticated next-generation designs as quickly as possible, in particular in Mobile, Telecom and Consumer applications."

STMicroelectronics adoption of Catapult C Synthesis libraries comes after several years of close collaboration with Mentor Graphics. The two companies worked together to generate custom libraries, develop test programs, and achieve integration with downstream implementation tools in STMicroelectronics ASIC design kit. STMicroelectronics has joined the Catapult Silicon Vendor Partners (SVP) Program, which allows ASIC, FPGA (field programmable gate array), and semiconductor foundry companies to provide certified Catapult C Synthesis libraries to their customers. Under the terms of the program, Mentor Graphics and STMicroelectronics performed
extensive testing to ensure the quality and reliability of Catapult libraries with STMicroelectronics ASIC technology. As a result, STMicroelectronics customers can expect increased efficiency and decreased risk if they choose to use Catapult C Synthesis to implement hardware in STMicroelectronics ASIC technology.

"As a recognized leader in advanced IC design methodologies, STs decision to develop, certify and distribute Catapult C Synthesis libraries as part of their standard ASIC design kit represents a powerful endorsement of our product family's quality and maturity among electronic system level (ESL) design tools," said Simon Bloch, general managerof the Design Creation and Synthesis division for Mentor Graphics. "We are very pleased that our collaboration with STMicroelectronics has resulted in such a prestigious honor, and hope that this is the first of many joint
successes to come."


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