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Electronics Production | October 16, 2007

IMEC and Target Compiler in collaboration

IMEC and Target Compiler Technologies, Spcialist on EDA tools for the design and programming of application-specific processors (ASIPs have entered into a collaboration agreement aiming at advancing the state-of-the-art in ultralow power system-on-chip design.
The new collaboration fits in IMEC’s R&D activities on wireless autonomous transducer solutions at the Holst Centre and will be centered around Target’s Chess/Checkers tool-suite for ASIP design.

This collaboration fits in IMEC's R&D activities on wireless autonomous transducer solutions, carried out at the Holst Centre in Eindhoven, the Netherlands, and will be centred around Target's tool suite for application-specific processor design.

As part of the agreement, IMEC and residents of partners of the wireless autonomous transducer solutions program will have access to Target’s Chess/Checkers tool suite to design and program novel ultra-low power ASIP cores that will become the computational heart of new autonomous wireless sensor nodes. Power efficiency of several hundred MOPS/mW is targeted. Also, IMEC and Target will jointly investigate new design methodologies to push the power efficiencies of programmable architectures to the next level.

Multi-processor system-on-chip platforms based on ASIPs hold the promise of meeting the ultra-low power challenges of wireless sensor nodes, thanks to their inherent parallelism and architectural specialization.

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