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© luchschen dreamstime.com Components | September 19, 2013

TSMC and OIP Ecosystem Partners deliver three new Flows

TSMC has released three silicon-validated Reference Flows within the Open Innovation Platform (OIP) that enable 16FinFET systems-on-chip (SoC) designs and 3D chip stacking packages.
Leading Electronic Design Automation (EDA) vendors collaborated with TSMC to develop and validate all these flows through multiple silicon test vehicles.

The new Reference Flows are:
1. TSMC’s 16FinFET Digital Reference Flow, providing comprehensive technology support to address post-planar design challenges including extraction, quantized pitch placement, low-vdd operation, electromigration, and power management.

2. The 16FinFET Custom Design Reference Flow, offering full custom transistor-level design and verification including analog, mixed-signal, custom digital and memory.

3. The 3D IC Reference Flow, addressing emerging vertical integration challenges with true 3D stacking.

“These Reference Flows give designers immediate access to TSMC’s 16FinFET technology and pave the way to 3D IC Through-Transistor-Stacking (TTS) technology,” said TSMC Vice President of R&D, Dr. Cliff Hou. “Delivering our most advanced silicon and manufacturing technologies as early and completely as possible to our customers is a major milestone for TSMC and its OIP design ecosystem partners.”

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