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Embedded | July 05, 2012

Cadence collaborates with Brite Semi

Brite and Cadence plan to integrate the DDR PHY IP with I/Os for implementation on SMIC 130nm, 65nm, 55nm, and 40nm process technologies.
"The collaboration between Cadence and Brite places market-leading memory IP in the SMIC ecosystem providing SoC designers with easy access to this low-power, high-performance, technology," said Martin Lund, senior vice president of Research and Development, SoC Realization Group at Cadence. "We look forward to a close and on-going relationship with Brite to continue developing leading-edge memory solutions driving higher levels of performance and functionality in today's mobile devices."

"We are pleased to extend our partnership with Cadence to deliver the superior wide range DDR PHY solution of our ASIC products," said Dr. Charlie Zhi, Chief Executive Officer at Brite Semiconductor. "To successfully deliver customized SoCs, we must have an area efficient, configuration flexible, and multi-standard support including DDR2, DDR3, LPDDR1, LPDDR2, memory PHY solution in current and advanced SMIC process technology nodes. This partnership is affording Brite the opportunity to seamlessly integrate DDR PHY, and corresponding features, into ASIC products and providing our customers a significantly competitive advantage. Furthermore, this collaboration would create the opportunity for rapid time to market execution, and reduce the entry barrier for designing in advanced process nodes."
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