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Components | July 18, 2011

Tapeout of first 20nm test chip using Synopsys

Synopsys' design enablement collaboration with Samsung Electronics has achieved a critical milestone with the successful tapeout of the first 20-nanometer (nm) test chip based on Samsung's High-k metal gate (HKMG) process technology.

The test chip was implemented using Synopsys' Galaxy Implementation Platform, including the Design Compiler synthesis, IC Compiler place-and-route, In-Design physical verification with IC Validator, StarRC extraction and PrimeTime signoff tools. The 20-nm tapeout represents the outcome of early R&D collaboration between Samsung and Synopsys aimed at developing and validating a comprehensive design implementation infrastructure for the next generation of 20-nm gigascale integrated circuits (ICs). Key 20-nm design enablement innovations developed as part of the collaboration include modeling of new device structures, double-patterning-aware place-and-route and In-Design physical verification technology, and coding of advanced routing and design rule checking (DRC). Together, these innovations enable fast routing throughput while delivering full compliance with thousands of complex rules and manufacturable routing patterns. "Leveraging its deep know-how in advanced process and design technologies, as well as its long-standing partnership with ISDA, Samsung is quickly readying its 20-nanometer solution," said Dr. Kyu-Myung Choi, vice president of System LSI infrastructure design center, Device Solutions, Samsung Electronics. "We are collaborating closely with Synopsys to enable the timely availability of innovative components in our 20-nanometer design infrastructure. Synopsys' technology leadership enabled us to quickly implement and validate our first 20-nanometer test chip. The successful tapeout of this test chip marks a critical milestone towards design readiness for our 20-nanometer process technology." "Samsung has long been a valued partner who has actively worked with Synopsys on new technology development" said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "This achievement in 20-nanometer design enablement is an example of our early and close collaboration, and demonstrates that we can provide innovative EDA solutions at the right time to meet the design needs of the 20-nanometer process technology. We are committed to continuing our collaboration with Samsung so we can ensure our mutual customers have the necessary infrastructure to successfully design products at today's most advanced technology process node."
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