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Electronics Production | May 31, 2007

HARDI teams with LSI

HARDI Electronics today announced a solution to high speed interfaces for ASIC prototyping with a HapsTrak compatible SerDes (high speed serial transceiver) daughter board containing an ASIC SerDes evaluation chip from LSI.
HapsTrak guarantees that this SerDes daughter board will be compatible with all previous and future generations of HAPS (HARDI ASIC Prototyping System) motherboards.

Increasing data transmission rates is making it more difficult to verify and prototype ASIC based storage and communication systems. For example, prototyping SerDes in an FPGA has significant limitations. Not only are the electrical and logical behaviors different between ASIC and FPGA
SerDes, but the RTL verified in the prototype also requires special attention to adapt to the functionality differences.

A more accurate alternative is to prototype using a native ASIC SerDes in an evaluation chip. The engineering teams at HARDI and LSI have worked together to develop a HapsTrak compatible SerDes Daughter Board hosting the LSI evaluation chip. All high speed PCB layout issues have also been addressed. For example, signal integrity is of paramount importance. Detailed attention is required for the prototyping PCB and cabling designs including clean power supplies and grounding, controlled impedance transmission lines and low noise. Cross-talk, reflections, impedance matching, and length matching are some of the layout issues that must be dealt with.

The SerDes Daughter Board supports PCIe + PIPE, SAS, SATA, Fibre Channel, InfiniBand, and GigE.

"We are seeing more and more customers run into significant issues with high speed interfaces while prototyping," said Lars-Eric Lundgren, CEO of HARDI. "We are thrilled to have had the opportunity to work closely with LSI to solve this problem and offer such a robust high-speed connectivity solution to our ASIC prototyping customers. We continually to strive to provide more value to our customers by getting them prototyping faster with more accurate ASIC functionality and this new daughter board is an extension of that goal."

Mike Casey, Director of Technical Marketing at LSI said, "Prototype based verification is being used more frequently in our own ASSP programs. HARDI's implementation of our SerDes opens up a flexible prototyping environment, which we can extend to our ASIC customers. Having a prototype
that behaves as expected in the final ASIC reduces verification risks with PHY and link layer IP's and speeds in-system electrical testing. Our engineering teams have cooperated on this daughter board to help our mutual customers bring better designs to market faster."

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