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Electronics Production | February 09, 2007

Getting the most out of<br>ASIC prototyping with FPGAs

Over the past 18 months, there has been a growing adoption of the use of FPGAs to prototype ASICs as part of an ASIC verification methodology.
With the development costs for ASICs skyrocketing – a typical 90nm ASIC/SoC design tape-out today costs around $20M; a 90nm mask set alone costs over $1M; and total development cost for a 45nm SoC is expected to top $40M – it is clear to see why avoiding a respin by prototyping with FPGAs is attractive.

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