Cadense wins DesignVision award

First Encounter GPS integrates silicon virtual prototyping and second-generation global physical synthesis technology into a single environment optimized for very large-scale system-on-chip design. Building on the Cadence Encounter digital IC design platform's recognized leadership in the market, First Encounter GPS leverages Encounter RTL Compiler's global-focused synthesis methods to close timing quickly even on very large circuit blocks. This in turn supports the rapid design and assembly of densely integrated ICs common in high end graphics, networking and processor applications. First Encounter GPS supports RTL-to-placed gates and netlist-to-placed gates design flows. "We are very proud that the International Engineering Consortium selected us," said Wei-Jin Dai, platform vice president, digital IC implementation at Cadence. "This is further validation that First Encounter GPS's physical synthesis is living up to the reputation it began building last year. The growing number of high end tapeouts and now this award reflect our commitment to helping Cadence customers put very complex and differentiated electronics into silicon, ahead of their competitors. " With over 100 90-nanometer designs either taped out or underway, and multiple 65-nanometer projects in progress, First Encounter GPS provides a production-proven path to high end silicon.