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11
October
2011

EV Group and Fraunhofer IZM-ASSID cooperate

EV Group (EVG) has established an agreement with world-renowned research institute Fraunhofer IZM- ASSID to jointly develop high-volume manufacturing processes for 3D IC integration applications.
Specifically, the two organizations will leverage their expertise to extend temporary bonding and debonding processes to support chip-to-wafer bonding with higher levels of topography (up to 600 microns thick)—a critical step in ramping 3D IC technology to volume production. The joint-development project will take place in ASSID's leading-edge facility in Dresden, Germany—the first Fraunhofer Center with a 300-mm line dedicated to developing processes for high-volume 3D IC manufacturing and prototyping.

"The growing need for 'More than Moore' approaches to extend semiconductor performance makes it ever-more important to develop and commercialize new processes to enable 3D IC integration," stated M. Jurgen Wolf, manager of Fraunhofer IZM-ASSID. "We look forward to strengthening our partnership with EVG to new levels as we work together to develop and optimize processes critical to enabling 3D IC production."

"The growing need for 'More than Moore' approaches to extend semiconductor performance makes it ever-more important to develop and commercialize new processes to enable 3D IC integration." M. Jurgen Wolf, manager of Fraunhofer IZM-ASSID
Chip-to-wafer bonding, where chips from one wafer are diced and joined to another wafer, has emerged as a promising method for enabling 3D IC integration. In chip-to-wafer bonding, chips can be tested before bonding to ensure that only known good die are joined together—enabling higher device yields.

In addition, devices with heterogeneous technologies (different sizes, feature dimensions, etc.) can be bonded together to achieve 3D die stacks with a broad range of functionality (logic, memory, mixed signal, photonics, etc.) in the smallest possible space. Currently, the most advanced temporary bonding/debonding processes can support bonded wafers with topographies up to 100 microns thick.

However, as the complexity of the die structures continues to increase, the topography of the bonded wafers will increase in thickness as well—requiring continuous advances in rigid backgrinding support for wafer thinning, as well as low vertical force debonding to avoid defects during the debonding process.

"As a leader in advanced semiconductor R&D, Fraunhofer IZM-ASSID is constantly pushing the envelope on new process technologies needed to keep the semiconductor industry on its roadmap," stated Markus Wimplinger, corporate technology development and IP director for EVG. "Their proven track record of delivering industrial solutions coupled with their expertise in wafer-level packaging makes them an ideal partner for jointly developing advanced processes, including temporary bonding and debonding, to accelerate the production of 3D ICs."

Under the terms of the agreement, EVG will provide its extensive expertise in 3D IC tooling and process development, particularly in wafer debonding.

Fraunhofer IZM-ASSID will in turn lend its industry-leading expertise in wafer-level packaging and system integration technologies, access to test samples and demonstrator materials, and its established network with other research institutes and universities in the field of advanced system integration to ensure that the developed processes fully meet the industry's requirements for 3D process integration.

Process development work will be accomplished using EVG850 TB/DB systems already installed at Fraunhofer IZM-ASSID's facility.
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