Freescale, Photronic to collaborate

The joint exploratory development aims at extending the life of current-generation lithography tools to ensure the production of chips that are small, fast and powerful enough to enable pervasive computing and advanced wireless applications. "The advanced development by Freescale and Photronics will be a significant influence on mass production of 65-nmCMOS devices and below," said Dr. Joe Mogab, senior technical fellow and director of the Advanced Products Research and Development Laboratory for Freescale. "Our joint advanced lithography work with Photronics will helpprovide us with the necessary RET improvements to provide the best and most cost-effective solutions for our customers businesses." The collaboration is a three-year commitment that began in Q404. Freescale supplies representative patterns and unique analytical support, wafer imaging and data analysis, while Photronics supplies test reticles and reticle fabrication details. Christopher Progler, PhD, Photronics CTO, said, "There are inherent and interrelated challenges in design, photomask and lithography as semiconductor technology transitions to 90-nm, 65-nm and beyond. Our alliance with Freescale will play a significant role in expediting our customers time-to-silicon, maintaining cost and improving chip yield." The resolution limit of optical lithography generally has been considered to be the wavelength of the exposure light. However, by employing RET, the minimum printable feature size can be reduced to less than 50 percent of the exposure wavelength. In a departure from standard industry practice, Freescale worked with Photronics to test multiple RET processes: six percent embedded attenuated phase shift masks (EAPSM), complementary phase shift masks (CPSM) and chromeless phase lithography (CPL). They found little statistical differences between the methods with respect to critical dimension control achieved at the 65-nm node. However, the researchers did find significant differences in other important metrics associated with specific RET implementation such as line-edge roughness and 2D image acuity. The companies have joined efforts to explore how these differences and other process improvements can be used to extend RET applications.