Panasonic and Renesas sign collaboration agreement

The two companies are confident that their 32-nm node transistor technology and other advances can soon be applied to products in mass production. It is anticipated that SoCs at the 32-nm node will deliver lower cost and improved performance enabled by miniaturization of their design rules, yet there are many technical issues that need to be solved. In particular, it is necessary to introduce new materials and develop new technologies to break through barriers to further integration, such as transistor gate leakage and inconsistent electrical characteristic problems, which are often found in existing technologies. Introducing new materials is technically difficult; however, the technology challenges in achieving acceptable transistor performance at the 32-nm node are more formidable than they were at previous-generation process nodes. The two partners have been working on the joint development of next-generation SoC technology, even before the establishment of Renesas Technology. Their joint development work has yielded impressive results until now. They developed a 130-nm DRAM composite process in 2001, a 90-nm SoC process in 2002, a 90-nm DRAM composite process in 2004, a 65-nm SoC process in 2005, and a 45-nm SoC process in 2007. The latest development on the new 32-nm fabrication process will be applied to SoCs for advanced mobile and digital home appliance products. Building on their accumulated technology expertise and resulted new advances, as well as their successful partnership of many years, Panasonic and Renesas Technology hope to continue efficiently developing the advanced process technology that can be quickly moved to mass production respectively.