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© aydindurdu dreamstime.com Components | May 12, 2016

Cypress adopts Cadence design tools 40nm automotive chips

Cypress Semiconductor has selected the full Cadence RTL-to-signoff digital design flow and complete Spectre circuit simulation platform for all of its 40nm automotive chip designs.
The Cadence digital flow consists of the Innovus Implementation System, the Genus Synthesis Solution, the Tempus Timing Signoff Solution, Conformal Low Power and the Quantus QRC Extraction Solution. These tools collectively enabled Cypress to achieve improved individual tool throughput and productivity gains. Specifically, the Innovus Implementation System provided Cypress with significant power, performance and area (PPA) benefits. In particular, low power was a critical requirement for the Cypress 40nm automotive designs.

“We’re always up against tight deadlines to deliver innovative and reliable designs to our automotive customers,” said Dragomir Nikolic, worldwide CAD director at Cypress. “While looking at the digital offerings from Cadence, specifically the Innovus Implementation System and the Tempus Timing Signoff Solution, we've seen an opportunity to improve our quality of results while significantly reducing cycle time. We know these offerings are state of the art in the EDA industry, and we are eager to see the tools in action on our 40nm platform. In addition to low power, reliability and low parts per billion (PPB) defect rates are critical for us. The Innovus Implementation System routing capability enables us to drive those defects even lower for our automotive customers.”
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