Ad
Ad
Ad
Ad
Ad
Ad
© luchschen dreamstime.com Embedded | May 29, 2014

Synopsys and TSMC collaborate

Synopsys, Inc. announced the validation of DesignWare IP in the TSMC 16-nanometer (nm) FinFET process technology.
"TSMC's longstanding collaboration with Synopsys has enabled us to offer designers access to a broad portfolio of high-quality IP solutions for a wide range of TSMC processes," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "Working with Synopsys on the development of the DesignWare Interface, Logic Library and Embedded Memory IP for TSMC's advanced 16-nm FinFET process extends our long history of success, and puts Synopsys on track to deliver quality IP in the 16FF+ process to reduce integration risk and accelerate time-to-volume production for our mutual customers."

"Synopsys' close collaboration with TSMC has enabled us to successfully deliver silicon-proven IP in TSMC's advanced 16-nm FinFET process and help designers accelerate the adoption of FinFET technology for higher-performance and more power-efficient SoCs," said John Koeter, vice president of marketing for IP and systems at Synopsys. "The successful DesignWare IP silicon results, combined with the experience gained from developing IP for the 16-nm FinFET process, put us in a strong position to deliver on our 16FF+ roadmap, enabling designers to gain the full benefits of the advanced node and bring differentiated products to market faster."

Comments

Please note the following: Critical comments are allowed and even encouraged. Discussions are welcome. Verbal abuse, insults and racist / homophobic remarks are not. Such comments will be removed.
Further details can be found here.
Ad
Ad
Load more news
February 08 2018 5:15 pm V9.2.4-2