© 3quarks dreamstime.com
Components |
Due to its performance, power, intra-die variability and lower retention voltage over the planar CMOS process, the FinFET process is gaining significant interest from designers. This process qualification vehicle will provide early silicon data, enabling UMC to tune its 14-nm FinFET process and Synopsys to refine its DesignWare IP portfolio for optimal power, performance and area. It also provides data to enable better correlation of the FinFET simulation models to the silicon results. This is the first milestone of an ongoing collaboration to validate UMC's 14-nm FinFET processes using DesignWare IP solutions. "The successful tape-out of this qualification vehicle is a significant milestone for UMC," said Arthur Kuo, UMC vice president in charge of the company's corporate marketing division. "Our goal is to provide customers with a highly competitive FinFET technology solution that will help them maintain their products at the leading-edge. We selected Synopsys for this important collaboration based on their FinFET experience and expertise as well as their track record of developing high-quality DesignWare IP in the most advanced nodes. The results of this collaboration will yield significant benefits to the design community in the areas of power, performance and cost." Synopsys' DesignWare Logic Library IP and StarRC Parasitic Extraction Tool Synopsys' FinFET-ready DesignWare Logic Library IP portfolio consists of high-speed, high-density and low-power standard cell libraries that include multiple voltage threshold implementations and support multi-channel gate lengths to minimize leakage power. In addition, the available Power Optimization Kits (POKs) and Engineering Change Order (ECO) Kits deliver outstanding performance with low power and small area, meeting the speed and density requirements of advanced SoCs. The StarRC parasitic extraction tool offers advanced extraction capabilities at 14 nm, based on precise 3-D modeling of the new parasitics found in FinFET devices. Due to its unique ability to describe the exact silicon profile of FinFET transistors, StarRC's embedded field solver generates highly accurate device model parasitics which enable 14-nm IP developers to optimize their designs for maximum performance and lowest power. Synopsys' Galaxy Implementation Platform also provides designers with a full suite of implementation tools that are FinFET-ready. "Synopsys continues to lead the market in the development of IP and tools for FinFET technologies," said John Koeter, vice president of marketing for IP and systems at Synopsys. "Our collaboration with UMC further demonstrates our mutual commitment to delivering proven IP and tools that help designers lower integration risk and speed their time-to-volume production."
Synopsys and UMC collaborate
Synopsys, Inc. and United Microelectronics's collaboration between the two companies has resulted in the successful tapeout of UMC's first process qualification vehicle in its 14-nanometer (nm) FinFET process utilizing Synopsys' DesignWare Logic Library IP portfolio and StarRC parasitic extraction solution, a part of the Galaxy Implementation Platform.
Due to its performance, power, intra-die variability and lower retention voltage over the planar CMOS process, the FinFET process is gaining significant interest from designers. This process qualification vehicle will provide early silicon data, enabling UMC to tune its 14-nm FinFET process and Synopsys to refine its DesignWare IP portfolio for optimal power, performance and area. It also provides data to enable better correlation of the FinFET simulation models to the silicon results. This is the first milestone of an ongoing collaboration to validate UMC's 14-nm FinFET processes using DesignWare IP solutions. "The successful tape-out of this qualification vehicle is a significant milestone for UMC," said Arthur Kuo, UMC vice president in charge of the company's corporate marketing division. "Our goal is to provide customers with a highly competitive FinFET technology solution that will help them maintain their products at the leading-edge. We selected Synopsys for this important collaboration based on their FinFET experience and expertise as well as their track record of developing high-quality DesignWare IP in the most advanced nodes. The results of this collaboration will yield significant benefits to the design community in the areas of power, performance and cost." Synopsys' DesignWare Logic Library IP and StarRC Parasitic Extraction Tool Synopsys' FinFET-ready DesignWare Logic Library IP portfolio consists of high-speed, high-density and low-power standard cell libraries that include multiple voltage threshold implementations and support multi-channel gate lengths to minimize leakage power. In addition, the available Power Optimization Kits (POKs) and Engineering Change Order (ECO) Kits deliver outstanding performance with low power and small area, meeting the speed and density requirements of advanced SoCs. The StarRC parasitic extraction tool offers advanced extraction capabilities at 14 nm, based on precise 3-D modeling of the new parasitics found in FinFET devices. Due to its unique ability to describe the exact silicon profile of FinFET transistors, StarRC's embedded field solver generates highly accurate device model parasitics which enable 14-nm IP developers to optimize their designs for maximum performance and lowest power. Synopsys' Galaxy Implementation Platform also provides designers with a full suite of implementation tools that are FinFET-ready. "Synopsys continues to lead the market in the development of IP and tools for FinFET technologies," said John Koeter, vice president of marketing for IP and systems at Synopsys. "Our collaboration with UMC further demonstrates our mutual commitment to delivering proven IP and tools that help designers lower integration risk and speed their time-to-volume production."
