28nm low-power test chip with Tensilica processor and RacyICs

The chip is able to operate in a wide voltage and frequency range from 0.7V to 1.1V and 90 MHz to 1 GHz. Within that range, the optimal voltage/frequency combination is determined adaptively based on a new hardware performance monitor concept. The complete baseline IP (standard cell libraries, IO cells, SRAM blocks, PLL) was developed by the university team, who also did logic synthesis, place and route and sign-off of the test chip. "Our ability to successfully realize microchips in advanced technologies is a result of a long-term strategy to build an experienced team, which covers all aspects of analog, digital and mixed-signal IC design," stated Professor René Schüffny, TU Dresden. "This accumulated engineering competence is one key enabler for TU Dresden's leading-edge research in the field of complex systems based on advanced electronics." The chip has been developed within the frame of the CoolRF28 project. This project is part of the Leading-Edge Cluster "Cool Silicon," which is sponsored by the German Federal Ministry of Education and Research (BMBF) within the scope of its Leading-Edge Cluster Competition. In the "Cool Silicon" cluster, universities, research institutes, small and medium enterprises (SMEs) and big corporations closely cooperate in numerous projects on the next generation of energy-efficient electronics. "We're very impressed by the high research and engineering competence of the TU Dresden team," stated Frank Dresig, Globalfoundries' European Field Engineering Manager. "The chip directly shows the capabilities of our advanced 28nm SLP process for implementation of ultra low-power SoCs for consumer applications." The test chip's power management is based on an IP for adaptive voltage and frequency scaling provided by RacyICs, a start-up company offering design and implementation services. "The close cooperation with TU Dresden and Globalfoundries helps us to develop world-class services and IP products in advanced technology nodes," stated Holger Eisenreich, RacyICs' Managing Director. "Because of high risks and costs, it is almost impossible for SMEs to enter this market without such cooperation." With assistance from Tensilica, the university team integrated an Xtensa LX4 DSP core to demonstrate the overall power reduction benefits from the combination of a 28nm low-power technology, adaptive power management and an advanced processor IP core. "Tensilica has had a long-standing relationship with the researchers at TU Dresden and congratulates them on this successful design effort," stated Chris Rowen, Tensilca's CTO. "Tensilica's Xtensa processor is a fundamental building block in TU Dresden's wireless communications architecture, and we are working together to proliferate know-how on configurable architectures to the worldwide design community."