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Components | February 23, 2012

World-first 11bit 250MSamples/s SAR ADC

Imec and Renesas Electronics report record ADC for next-generation high-bandwidth wireless receivers
Imec and Renesas Electronics Corporationreport an innovative SAR (successive-approximation register) ADC (analog to digital converter) with a spectacular improvement in power efficiency and speed, targeting wireless receivers for next-generation high-bandwidth standards such as LTE-advanced and the emerging generation of Wi-Fi (IEEE802.11ac).

SAR ADCs provide high power efficiencies as well as a small form factor, making this architecture attractive for a wide variety of wireless applications. SAR ADCs are frequently the preferred architecture for applications with moderate resolution and sampling frequencies.

However, wireless receivers for next-generation high bandwidth standards such as LTE-advanced and the new generations of Wi-Fi require much faster ADCs. This new SAR ADC architecture, developed by imec and Renesas Electronics, is an answer to the need for much faster low-power ADCs with small form factor.

The reported ADC is an ultra-low power (1.7mWatt) high resolution (11b) fully-dynamic, two-step interleaved pipelined SAR ADC achieving a record power efficiency of 10fJoule per conversion step at a sampling speed as high as 250MSamples/s. This is a spectacular increase of the speed and sampling frequency, which are both an order of magnitude better than state-of-the art available ADC IP blocks.

This result is obtained with a new converter architecture based on prior groundbreaking ADC designs from imec, cleverly exploiting the opportunities of modern advanced CMOS technologies. The design uses completely dynamic circuits, such that the power consumption scales linearly with the sampling frequency, and is implemented with a maximum amount of digital content, leaving the comparator as the only analog building block.

The ADC prototype has been manufactured in 40nm CMOS with a core chip area of 0.066mm2. Measurements show a DNL and INL of respectively 0.8/-0.5 and 1.1/-1.5 LSB. The dynamic performance is characterized by 62dB SNDR (10.0 ENOB) at 10MSamples/s, which is maintained up to 9.5 ENOB level for a sampling speed of up to 250MSamples/s. The power consumption is 6.9pJoule per conversion (70µWatt at 10MSamples/s, 1.7mWatt at 250MSamples/s), resulting in a spectacular energy efficiency of 7 to 10fJoule per conversion-step.

Also at ISSCC, imec and Renesas Electronics present a new way to connect the ADC architecture with the complete radio architecture. To improve the power efficiency of the total receiver system, and avoid issues related to large input capacitors in a voltage-domain ADC system, a 3.2-51.2mSiemens current domain variable-gain transconductor (VGA) was used to drive a charge-domain SAR ADC with no overhead, and as such minimize the overall system power consumption. A 10b 10-80MSamples/s VGA-ADC prototype in 40nm CMOS achieves 70dB DR while consuming less than 5.45mA from a 1.1V supply.

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