Conexant adopts Target’s IP Designer Tool-Suite

By using IP Designer, Conexant plans to deliver unprecedented efficiency in their programmable platforms, while retaining the benefits of programming in C. Sverrir Olafsson, VP of Engineering at Conexant, comments: “We needed optimized DSP IP cores for our next generation product lines, and we evaluated multiple avenues to address this need. IP Designer from Target Compiler Technologies allowed us to build our own highly-efficient DSP architectures within very well-contained development schedules and costs. The resulting optimized DSPs are well-tuned to the specific needs of our vertical markets and will provide greater efficiencies and better product differentiation for our customers.” IP Designer is an EDA tool-suite used by SoC designers to design, optimize and program DSPs and other such application-specific processor cores (ASIPs). The designer can easily describe ASIP architectures with performance and energy characteristics that are superior to commercially available processor IP (or may even approach the efficiency of hardwired data-paths). Using Target’s processor modeling language (nML) and the IP Designer tool-suite (which includes a highly optimizing C compiler, a cycle- or instruction-accurate instruction-set simulator, and a graphical/interactive debugging/profiling environment), designers can explore and fine-tune a processor architecture for performance and efficiency and then automatically generate low-power RTL and comprehensive verification suites. Conexant’s new DSPs will be programmable from C – enabling significant improvements in algorithm development and code portability and re-use. Mr. Olafsson noted that “the efficiency of Target’s C compiler allowed us to nearly eliminate assembly coding, which will help accelerate our time to market objectives. We were impressed by the level of support we received from Target throughout the entire development cycle.” Today, with its adoption of IP Designer, Conexant joins other Target customers in the audio domain such as GN Resound, NXP, Silicon Labs and SiTel. “More and more companies are finding that ASIP design tools provide a valuable opportunity to increase differentiation in their end products,” comments Gert Goossens, Target’s CEO. “IP Designer has dispelled the notion that only large teams can be successful in custom processor design. Instead, in engagements such as with Conexant, we have shown that impressive results can be attained with compact teams and compact schedules. You no longer have to choose between design optimality and time to market.”