Ad
Ad
Ad
Ad
Ad
Ad
Ad
Components | May 25, 2011

Imec and Atrenta develop exploration Flows for 3D ICs

Atrenta, in collaboration with imec’s 3D integration IIAP (industrial affiliation program), have jointly developed an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs.
A flow allowing robust, accurate partitioning and prototyping early in the design process is critical to make cost-effective 3D systems and to get them to market fast. The flow under development allows minimizing the number of design iterations, facilitating a cost- and time-effective search of the solution space.

3D stacked ICs are a promising technology for many designers. The main advantages are a reduced footprint with shorter and faster interconnects, increased system integration at a lower cost, and higher modularity and reuse. Examples of target applications include: products for mobile and high-performance applications, imagers, stacked DRAM, and solid-state drives.

To design innovative applications with 3D stacked dies, the ability to do early planning and partitioning is critical. The number of potential solutions for any given system design problem (e.g., front to front, front to back, silicon interposer, technology choice for slices, via configurations, partitioning, etc.) is very large. Exploring this solution space through multiple full designs is simply too expensive and time-consuming. This makes it critically important to perform robust, accurate partitioning and prototyping early in the design process, well before detailed implementation begins.

Comments

Please note the following: Critical comments are allowed and even encouraged. Discussions are welcome. Verbal abuse, insults and racist / homophobic remarks are not. Such comments will be removed.
Further details can be found here.
Ad
Ad
Load more news
October 16 2017 2:56 PM V8.8.6-2